File Manager

X7ROOT File Manager

Current Path: /usr/include/linux

📁 ..
📄 a.out.h(6.73 KB)
📄 acct.h(3.82 KB)
📄 acrn.h(16.29 KB)
📄 adb.h(1.11 KB)
📄 adfs_fs.h(993 B)
📄 affs_hardblocks.h(1.54 KB)
📄 agpgart.h(3.85 KB)
📄 aio_abi.h(3.32 KB)
📄 am437x-vpfe.h(3.59 KB)
📁 android
📄 apm_bios.h(3.6 KB)
📄 arcfb.h(213 B)
📄 arm_sdei.h(2.69 KB)
📄 aspeed-lpc-ctrl.h(1.74 KB)
📄 aspeed-p2a-ctrl.h(1.86 KB)
📄 atalk.h(1023 B)
📄 atm.h(7.7 KB)
📄 atm_eni.h(648 B)
📄 atm_he.h(406 B)
📄 atm_idt77105.h(955 B)
📄 atm_nicstar.h(1.25 KB)
📄 atm_tcp.h(1.58 KB)
📄 atm_zatm.h(1.5 KB)
📄 atmapi.h(952 B)
📄 atmarp.h(1.27 KB)
📄 atmbr2684.h(3.19 KB)
📄 atmclip.h(576 B)
📄 atmdev.h(7.5 KB)
📄 atmioc.h(1.61 KB)
📄 atmlec.h(2.33 KB)
📄 atmmpc.h(4.13 KB)
📄 atmppp.h(639 B)
📄 atmsap.h(4.85 KB)
📄 atmsvc.h(1.81 KB)
📄 audit.h(21.06 KB)
📄 auto_dev-ioctl.h(4.87 KB)
📄 auto_fs.h(6.28 KB)
📄 auto_fs4.h(451 B)
📄 auxvec.h(1.56 KB)
📄 ax25.h(2.76 KB)
📄 batadv_packet.h(19.87 KB)
📄 batman_adv.h(16.49 KB)
📄 baycom.h(883 B)
📄 bcm933xx_hcs.h(419 B)
📄 bfs_fs.h(1.86 KB)
📄 binfmts.h(776 B)
📄 bits.h(447 B)
📄 blkpg.h(904 B)
📄 blktrace_api.h(4.59 KB)
📄 blkzoned.h(6.34 KB)
📄 bpf.h(272.11 KB)
📄 bpf_common.h(1.33 KB)
📄 bpf_perf_event.h(529 B)
📄 bpfilter.h(465 B)
📄 bpqether.h(981 B)
📄 bsg.h(2.44 KB)
📄 bt-bmc.h(572 B)
📄 btf.h(5.46 KB)
📄 btrfs.h(29.85 KB)
📄 btrfs_tree.h(25.22 KB)
📁 byteorder
📄 cachefiles.h(1.61 KB)
📁 caif
📁 can
📄 can.h(11.23 KB)
📄 capability.h(13.17 KB)
📄 capi.h(3.05 KB)
📄 cciss_defs.h(3.2 KB)
📄 cciss_ioctl.h(2.7 KB)
📄 ccs.h(767 B)
📄 cdrom.h(28.87 KB)
📄 cec-funcs.h(53.14 KB)
📄 cec.h(40.47 KB)
📄 cfm_bridge.h(1.42 KB)
📄 cgroupstats.h(2.17 KB)
📄 chio.h(5.16 KB)
📁 cifs
📄 close_range.h(377 B)
📄 cm4000_cs.h(1.76 KB)
📄 cn_proc.h(4.05 KB)
📄 coda.h(17.79 KB)
📄 coff.h(12.25 KB)
📄 connector.h(2.2 KB)
📄 const.h(987 B)
📄 coresight-stm.h(747 B)
📄 cramfs_fs.h(3.47 KB)
📄 cryptouser.h(5.2 KB)
📄 cuda.h(905 B)
📄 cxl_mem.h(7.73 KB)
📄 cycx_cfm.h(2.92 KB)
📄 dcbnl.h(24.7 KB)
📄 dccp.h(6.29 KB)
📄 devlink.h(22.77 KB)
📄 dlm.h(2.49 KB)
📄 dlm_device.h(2.48 KB)
📄 dlm_netlink.h(1.13 KB)
📄 dlm_plock.h(894 B)
📄 dlmconstants.h(4.96 KB)
📄 dm-ioctl.h(11.48 KB)
📄 dm-log-userspace.h(14.83 KB)
📄 dma-buf.h(5.12 KB)
📄 dma-heap.h(1.36 KB)
📄 dn.h(4.53 KB)
📄 dns_resolver.h(3.86 KB)
📄 dpll.h(8.56 KB)
📄 dqblk_xfs.h(9.17 KB)
📁 dvb
📄 edd.h(5.47 KB)
📄 efs_fs_sb.h(2.17 KB)
📄 elf-em.h(2.57 KB)
📄 elf-fdpic.h(1.1 KB)
📄 elf.h(14.69 KB)
📄 errno.h(23 B)
📄 errqueue.h(1.94 KB)
📄 erspan.h(1.03 KB)
📄 ethtool.h(101.42 KB)
📄 ethtool_netlink.h(6.17 KB)
📄 ethtool_netlink_generated.h(19.17 KB)
📄 eventfd.h(264 B)
📄 eventpoll.h(2.84 KB)
📄 f2fs.h(3.22 KB)
📄 fadvise.h(842 B)
📄 falloc.h(3.56 KB)
📄 fanotify.h(7.7 KB)
📄 fb.h(16.09 KB)
📄 fcntl.h(4.22 KB)
📄 fd.h(11.83 KB)
📄 fdreg.h(5.24 KB)
📄 fib_rules.h(1.99 KB)
📄 fiemap.h(2.71 KB)
📄 filter.h(2.16 KB)
📄 firewire-cdev.h(43.2 KB)
📄 firewire-constants.h(3.16 KB)
📄 fou.h(819 B)
📄 fpga-dfl.h(8.52 KB)
📄 fs.h(12.88 KB)
📄 fscrypt.h(6.41 KB)
📄 fsi.h(2.2 KB)
📄 fsl_hypervisor.h(7.13 KB)
📄 fsl_mc.h(734 B)
📄 fsmap.h(4.29 KB)
📄 fsverity.h(3.11 KB)
📄 fuse.h(25.36 KB)
📄 futex.h(5.98 KB)
📄 gameport.h(897 B)
📄 gen_stats.h(1.49 KB)
📄 genetlink.h(2.19 KB)
📁 genwqe
📄 gfs2_ondisk.h(14.43 KB)
📄 gpio.h(19.46 KB)
📄 gsmmux.h(4.4 KB)
📄 gtp.h(734 B)
📄 handshake.h(1.61 KB)
📄 hash_info.h(971 B)
📁 hdlc
📄 hdlc.h(637 B)
📄 hdlcdrv.h(2.84 KB)
📄 hdreg.h(22.17 KB)
📄 hid.h(2.04 KB)
📄 hiddev.h(6.2 KB)
📄 hidraw.h(1.95 KB)
📄 hpet.h(743 B)
📁 hsi
📄 hsr_netlink.h(1.08 KB)
📄 hw_breakpoint.h(742 B)
📄 hyperv.h(10.89 KB)
📄 i2c-dev.h(1.83 KB)
📄 i2c.h(6.73 KB)
📄 i2o-dev.h(11.28 KB)
📄 i8k.h(1.49 KB)
📄 icmp.h(4.67 KB)
📄 icmpv6.h(4.2 KB)
📄 idxd.h(9.11 KB)
📄 if.h(10.67 KB)
📄 if_addr.h(1.84 KB)
📄 if_addrlabel.h(721 B)
📄 if_alg.h(1.53 KB)
📄 if_arcnet.h(3.63 KB)
📄 if_arp.h(6.41 KB)
📄 if_bonding.h(5.02 KB)
📄 if_bridge.h(20.27 KB)
📄 if_cablemodem.h(986 B)
📄 if_eql.h(1.32 KB)
📄 if_ether.h(8.21 KB)
📄 if_fc.h(1.7 KB)
📄 if_fddi.h(4.27 KB)
📄 if_hippi.h(4.14 KB)
📄 if_infiniband.h(1.22 KB)
📄 if_link.h(52.92 KB)
📄 if_ltalk.h(210 B)
📄 if_macsec.h(6.35 KB)
📄 if_packet.h(7.99 KB)
📄 if_phonet.h(424 B)
📄 if_plip.h(660 B)
📄 if_ppp.h(29 B)
📄 if_pppol2tp.h(3.23 KB)
📄 if_pppox.h(4.76 KB)
📄 if_slip.h(872 B)
📄 if_team.h(2.54 KB)
📄 if_tun.h(4 KB)
📄 if_tunnel.h(5.36 KB)
📄 if_vlan.h(1.79 KB)
📄 if_x25.h(881 B)
📄 if_xdp.h(5.29 KB)
📄 ife.h(351 B)
📄 igmp.h(2.99 KB)
📁 iio
📄 ila.h(1.22 KB)
📄 in.h(10.24 KB)
📄 in6.h(7.36 KB)
📄 in_route.h(936 B)
📄 inet_diag.h(4.9 KB)
📄 inotify.h(3.21 KB)
📄 input-event-codes.h(29.5 KB)
📄 input.h(15.84 KB)
📄 io_uring.h(20.4 KB)
📄 ioctl.h(163 B)
📄 iommufd.h(36.45 KB)
📄 ioprio.h(4.08 KB)
📄 ip.h(4.7 KB)
📄 ip6_tunnel.h(1.91 KB)
📄 ip_vs.h(13.8 KB)
📄 ipc.h(2.05 KB)
📄 ipmi.h(15.08 KB)
📄 ipmi_bmc.h(488 B)
📄 ipmi_msgdefs.h(3.35 KB)
📄 ipmi_ssif_bmc.h(441 B)
📄 ipsec.h(947 B)
📄 ipv6.h(4.07 KB)
📄 ipv6_route.h(1.86 KB)
📄 ipx.h(2.29 KB)
📄 irqnr.h(104 B)
📁 isdn
📄 iso_fs.h(6.33 KB)
📄 isst_if.h(14.92 KB)
📄 ivtv.h(2.95 KB)
📄 ivtvfb.h(1.18 KB)
📄 jffs2.h(6.66 KB)
📄 joystick.h(3.35 KB)
📄 kcm.h(822 B)
📄 kcmp.h(522 B)
📄 kcov.h(1.92 KB)
📄 kd.h(6.3 KB)
📄 kdev_t.h(383 B)
📄 kernel-page-flags.h(900 B)
📄 kernel.h(194 B)
📄 kernelcapi.h(1019 B)
📄 kexec.h(2.05 KB)
📄 keyboard.h(13.14 KB)
📄 keyctl.h(5.86 KB)
📄 kfd_ioctl.h(57.06 KB)
📄 kfd_sysfs.h(5.25 KB)
📄 kvm.h(47.24 KB)
📄 kvm_para.h(1001 B)
📄 l2tp.h(5.61 KB)
📄 landlock.h(11.55 KB)
📄 libc-compat.h(8.09 KB)
📄 limits.h(937 B)
📄 lirc.h(7.95 KB)
📄 llc.h(3.09 KB)
📄 loadpin.h(834 B)
📄 loop.h(3.32 KB)
📄 lp.h(4.09 KB)
📄 lsm.h(1.51 KB)
📄 lwtunnel.h(2.31 KB)
📄 magic.h(3.73 KB)
📄 major.h(4.55 KB)
📄 map_to_7segment.h(6.45 KB)
📄 matroxfb.h(1.43 KB)
📄 max2175.h(1.01 KB)
📄 mdio.h(23.78 KB)
📄 media-bus-format.h(6.75 KB)
📄 media.h(12.46 KB)
📄 mei.h(3.4 KB)
📄 mei_uuid.h(738 B)
📄 membarrier.h(9.14 KB)
📄 memfd.h(1.43 KB)
📄 mempolicy.h(2.51 KB)
📄 meye.h(2.47 KB)
📄 mii.h(9.27 KB)
📄 minix_fs.h(2.07 KB)
📁 misc
📄 mman.h(1.75 KB)
📁 mmc
📄 mmtimer.h(2.07 KB)
📄 module.h(293 B)
📄 mount.h(4.9 KB)
📄 mpls.h(2.25 KB)
📄 mpls_iptunnel.h(761 B)
📄 mptcp.h(3.67 KB)
📄 mptcp_pm.h(4.3 KB)
📄 mqueue.h(2.15 KB)
📄 mroute.h(5.78 KB)
📄 mroute6.h(4.81 KB)
📄 mrp_bridge.h(1.67 KB)
📄 msdos_fs.h(6.57 KB)
📄 msg.h(3.31 KB)
📄 mshv.h(7.93 KB)
📄 mtio.h(7.98 KB)
📄 nbd-netlink.h(2.35 KB)
📄 nbd.h(3.77 KB)
📄 ncsi.h(4.71 KB)
📄 ndctl.h(6.67 KB)
📄 neighbour.h(5.91 KB)
📄 net.h(2.04 KB)
📄 net_dropmon.h(2.85 KB)
📄 net_namespace.h(715 B)
📄 net_shaper.h(2.52 KB)
📄 net_tstamp.h(6.3 KB)
📄 netconf.h(614 B)
📄 netdev.h(5.65 KB)
📄 netdevice.h(2.2 KB)
📁 netfilter
📄 netfilter.h(1.69 KB)
📁 netfilter_arp
📄 netfilter_arp.h(445 B)
📁 netfilter_bridge
📄 netfilter_bridge.h(1.14 KB)
📄 netfilter_decnet.h(1.72 KB)
📁 netfilter_ipv4
📄 netfilter_ipv4.h(1.45 KB)
📁 netfilter_ipv6
📄 netfilter_ipv6.h(1.35 KB)
📄 netlink.h(12.09 KB)
📄 netlink_diag.h(1.49 KB)
📄 netrom.h(807 B)
📄 nexthop.h(3.97 KB)
📄 nfc.h(10.95 KB)
📄 nfs.h(4.36 KB)
📄 nfs2.h(1.43 KB)
📄 nfs3.h(2.4 KB)
📄 nfs4.h(6.54 KB)
📄 nfs4_mount.h(1.89 KB)
📄 nfs_fs.h(1.62 KB)
📄 nfs_idmap.h(2.19 KB)
📄 nfs_mount.h(2.09 KB)
📄 nfsacl.h(718 B)
📁 nfsd
📄 nfsd_netlink.h(1.95 KB)
📄 nilfs2_api.h(7.41 KB)
📄 nilfs2_ondisk.h(17.66 KB)
📄 nitro_enclaves.h(12.85 KB)
📄 nl80211.h(341.33 KB)
📄 nsfs.h(639 B)
📄 nubus.h(8 KB)
📄 nvme_ioctl.h(2.43 KB)
📄 nvram.h(532 B)
📄 omap3isp.h(20.36 KB)
📄 omapfb.h(5.78 KB)
📄 oom.h(511 B)
📄 openat2.h(1.42 KB)
📄 openvswitch.h(40.75 KB)
📄 packet_diag.h(1.63 KB)
📄 param.h(141 B)
📄 parport.h(3.56 KB)
📄 patchkey.h(892 B)
📄 pci.h(1.35 KB)
📄 pci_regs.h(61.89 KB)
📄 pcitest.h(920 B)
📄 perf_event.h(42.68 KB)
📄 personality.h(2.05 KB)
📄 pfkeyv2.h(10.32 KB)
📄 pfrut.h(7.8 KB)
📄 pg.h(2.34 KB)
📄 phantom.h(1.62 KB)
📄 phonet.h(4.57 KB)
📄 pidfd.h(256 B)
📄 pkt_cls.h(18.65 KB)
📄 pkt_sched.h(28.75 KB)
📄 pktcdvd.h(2.63 KB)
📄 pmu.h(5.32 KB)
📄 poll.h(22 B)
📄 posix_acl.h(1.22 KB)
📄 posix_acl_xattr.h(1.09 KB)
📄 posix_types.h(1.07 KB)
📄 ppdev.h(3.21 KB)
📄 ppp-comp.h(2.47 KB)
📄 ppp-ioctl.h(5.59 KB)
📄 ppp_defs.h(5.43 KB)
📄 pps.h(4.62 KB)
📄 pr.h(1.59 KB)
📄 prctl.h(10.81 KB)
📄 psample.h(2.57 KB)
📄 psci.h(5.21 KB)
📄 psp-dbc.h(5.16 KB)
📄 psp-sev.h(7.59 KB)
📄 ptp_clock.h(7.35 KB)
📄 ptrace.h(4.29 KB)
📄 qemu_fw_cfg.h(2.41 KB)
📄 qnx4_fs.h(2.27 KB)
📄 qnxtypes.h(624 B)
📄 qrtr.h(893 B)
📄 quota.h(6.16 KB)
📄 radeonfb.h(360 B)
📁 raid
📄 random.h(1.38 KB)
📄 rds.h(10.91 KB)
📄 reboot.h(1.31 KB)
📄 reiserfs_fs.h(775 B)
📄 reiserfs_xattr.h(533 B)
📄 remoteproc_cdev.h(1.08 KB)
📄 resource.h(2.32 KB)
📄 rfkill.h(6.45 KB)
📄 rio_cm_cdev.h(3.17 KB)
📄 rio_mport_cdev.h(9.11 KB)
📄 rkisp1-config.h(30.63 KB)
📄 romfs_fs.h(1.21 KB)
📄 rose.h(2.18 KB)
📄 route.h(2.28 KB)
📄 rpl.h(814 B)
📄 rpl_iptunnel.h(424 B)
📄 rpmsg.h(1.03 KB)
📄 rpmsg_types.h(288 B)
📄 rseq.h(4.79 KB)
📄 rtc.h(5.19 KB)
📄 rtnetlink.h(20.8 KB)
📄 rxrpc.h(4.81 KB)
📄 scc.h(4.52 KB)
📁 sched
📄 sched.h(6.12 KB)
📄 scif_ioctl.h(6.23 KB)
📄 screen_info.h(2.42 KB)
📄 sctp.h(35.18 KB)
📄 seccomp.h(5.6 KB)
📄 securebits.h(2.64 KB)
📄 sed-opal.h(5.29 KB)
📄 seg6.h(1.14 KB)
📄 seg6_genl.h(589 B)
📄 seg6_hmac.h(423 B)
📄 seg6_iptunnel.h(984 B)
📄 seg6_local.h(3.78 KB)
📄 selinux_netlink.h(1.17 KB)
📄 sem.h(2.98 KB)
📄 serial.h(4.9 KB)
📄 serial_core.h(4.93 KB)
📄 serial_reg.h(15.65 KB)
📄 serio.h(2.09 KB)
📄 sev-guest.h(2.47 KB)
📄 shm.h(3.71 KB)
📄 signal.h(388 B)
📄 signalfd.h(1.2 KB)
📄 smc.h(8.46 KB)
📄 smc_diag.h(2.88 KB)
📄 smiapp.h(1.03 KB)
📄 snmp.h(14.01 KB)
📄 sock_diag.h(1.27 KB)
📄 socket.h(919 B)
📄 sockios.h(6.69 KB)
📄 sonet.h(2.24 KB)
📄 sonypi.h(5.18 KB)
📄 sound.h(1.21 KB)
📄 soundcard.h(44.96 KB)
📁 spi
📄 stat.h(7.23 KB)
📄 stddef.h(1.69 KB)
📄 stm.h(1.25 KB)
📄 string.h(238 B)
📁 sunrpc
📁 surface_aggregator
📄 suspend_ioctls.h(1.4 KB)
📄 swab.h(6.76 KB)
📄 switchtec_ioctl.h(5.14 KB)
📄 sync_file.h(3.49 KB)
📄 synclink.h(8.77 KB)
📄 sysctl.h(25.3 KB)
📄 sysinfo.h(1.02 KB)
📄 target_core_user.h(4.52 KB)
📄 taskstats.h(8.13 KB)
📁 tc_act
📁 tc_ematch
📄 tcp.h(11.65 KB)
📄 tcp_metrics.h(1.94 KB)
📄 tdx-guest.h(1.27 KB)
📄 tee.h(13.09 KB)
📄 termios.h(172 B)
📄 thermal.h(3.23 KB)
📄 time.h(1.71 KB)
📄 time_types.h(1.24 KB)
📄 timerfd.h(936 B)
📄 times.h(278 B)
📄 timex.h(7.63 KB)
📄 tiocl.h(1.69 KB)
📄 tipc.h(8.62 KB)
📄 tipc_config.h(14.52 KB)
📄 tipc_netlink.h(9.17 KB)
📄 tipc_sockets_diag.h(468 B)
📄 tls.h(7.06 KB)
📄 toshiba.h(1.88 KB)
📄 tps6594_pfsm.h(1.13 KB)
📄 tty.h(1.55 KB)
📄 tty_flags.h(4.4 KB)
📄 types.h(1.6 KB)
📄 udf_fs_i.h(697 B)
📄 udmabuf.h(643 B)
📄 udp.h(1.65 KB)
📄 uhid.h(4.54 KB)
📄 uinput.h(9.04 KB)
📄 uio.h(732 B)
📄 uleds.h(798 B)
📄 ultrasound.h(4.46 KB)
📄 um_timetravel.h(3.87 KB)
📄 un.h(384 B)
📄 unistd.h(220 B)
📄 unix_diag.h(1.3 KB)
📁 usb
📄 usbdevice_fs.h(8.12 KB)
📄 usbip.h(1.47 KB)
📄 userfaultfd.h(10.68 KB)
📄 userio.h(1.48 KB)
📄 utime.h(223 B)
📄 utsname.h(669 B)
📄 uuid.h(28 B)
📄 uvcvideo.h(2.57 KB)
📄 v4l2-common.h(2.01 KB)
📄 v4l2-controls.h(94.59 KB)
📄 v4l2-dv-timings.h(30.39 KB)
📄 v4l2-mediabus.h(5.3 KB)
📄 v4l2-subdev.h(9.76 KB)
📄 vbox_err.h(7.09 KB)
📄 vbox_vmmdev_types.h(11.38 KB)
📄 vboxguest.h(9.15 KB)
📄 vdpa.h(1.74 KB)
📄 vduse.h(9.58 KB)
📄 version.h(374 B)
📄 veth.h(224 B)
📄 vfio.h(70.13 KB)
📄 vfio_ccw.h(1.29 KB)
📄 vfio_zdev.h(2.48 KB)
📄 vhost.h(8.24 KB)
📄 vhost_types.h(4.77 KB)
📄 videodev2.h(99.3 KB)
📄 virtio_9p.h(2 KB)
📄 virtio_balloon.h(5.16 KB)
📄 virtio_blk.h(9.75 KB)
📄 virtio_bt.h(910 B)
📄 virtio_config.h(4.36 KB)
📄 virtio_console.h(3.08 KB)
📄 virtio_crypto.h(13.56 KB)
📄 virtio_fs.h(573 B)
📄 virtio_gpio.h(1.7 KB)
📄 virtio_gpu.h(11.28 KB)
📄 virtio_i2c.h(1.16 KB)
📄 virtio_ids.h(3.7 KB)
📄 virtio_input.h(2.46 KB)
📄 virtio_iommu.h(3.84 KB)
📄 virtio_mem.h(6.99 KB)
📄 virtio_mmio.h(4.85 KB)
📄 virtio_net.h(14.72 KB)
📄 virtio_pci.h(7.3 KB)
📄 virtio_pcidev.h(2.33 KB)
📄 virtio_pmem.h(641 B)
📄 virtio_ring.h(8.52 KB)
📄 virtio_rng.h(265 B)
📄 virtio_scmi.h(637 B)
📄 virtio_scsi.h(5.94 KB)
📄 virtio_snd.h(12.86 KB)
📄 virtio_types.h(2.1 KB)
📄 virtio_vsock.h(3.27 KB)
📄 vm_sockets.h(7.18 KB)
📄 vm_sockets_diag.h(963 B)
📄 vmcore.h(455 B)
📄 vsockmon.h(1.84 KB)
📄 vt.h(2.99 KB)
📄 vtpm_proxy.h(1.68 KB)
📄 wait.h(682 B)
📄 watch_queue.h(3.41 KB)
📄 watchdog.h(2.28 KB)
📄 wireguard.h(7.57 KB)
📄 wireless.h(41.7 KB)
📄 wmi.h(1.72 KB)
📄 wwan.h(295 B)
📄 x25.h(3.48 KB)
📄 xattr.h(2.95 KB)
📄 xdp_diag.h(1.43 KB)
📄 xfrm.h(12.33 KB)
📄 xilinx-v4l2-controls.h(2.91 KB)
📄 zorro.h(3.22 KB)
📄 zorro_ids.h(29.26 KB)

Editing: mdio.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * linux/mdio.h: definitions for MDIO (clause 45) transceivers
 * Copyright 2006-2009 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef __LINUX_MDIO_H__
#define __LINUX_MDIO_H__

#include <linux/types.h>
#include <linux/mii.h>

/* MDIO Manageable Devices (MMDs). */
#define MDIO_MMD_PMAPMD		1	/* Physical Medium Attachment/
					 * Physical Medium Dependent */
#define MDIO_MMD_WIS		2	/* WAN Interface Sublayer */
#define MDIO_MMD_PCS		3	/* Physical Coding Sublayer */
#define MDIO_MMD_PHYXS		4	/* PHY Extender Sublayer */
#define MDIO_MMD_DTEXS		5	/* DTE Extender Sublayer */
#define MDIO_MMD_TC		6	/* Transmission Convergence */
#define MDIO_MMD_AN		7	/* Auto-Negotiation */
#define MDIO_MMD_C22EXT		29	/* Clause 22 extension */
#define MDIO_MMD_VEND1		30	/* Vendor specific 1 */
#define MDIO_MMD_VEND2		31	/* Vendor specific 2 */

/* Generic MDIO registers. */
#define MDIO_CTRL1		MII_BMCR
#define MDIO_STAT1		MII_BMSR
#define MDIO_DEVID1		MII_PHYSID1
#define MDIO_DEVID2		MII_PHYSID2
#define MDIO_SPEED		4	/* Speed ability */
#define MDIO_DEVS1		5	/* Devices in package */
#define MDIO_DEVS2		6
#define MDIO_CTRL2		7	/* 10G control 2 */
#define MDIO_STAT2		8	/* 10G status 2 */
#define MDIO_PMA_TXDIS		9	/* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET		10	/* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE	11	/* 10G PMA/PMD extended ability */
#define MDIO_PKGID1		14	/* Package identifier */
#define MDIO_PKGID2		15
#define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
#define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
#define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */
#define MDIO_PCS_EEE_ABLE2	21	/* EEE Capability register 2 */
#define MDIO_PMA_NG_EXTABLE	21	/* 2.5G/5G PMA/PMD extended ability */
#define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */
#define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
#define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
#define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */
#define MDIO_AN_EEE_ADV2	62	/* EEE advertisement 2 */
#define MDIO_AN_EEE_LPABLE2	63	/* EEE link partner ability 2 */
#define MDIO_AN_CTRL2		64	/* AN THP bypass request control */

/* Media-dependent registers. */
#define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */
#define MDIO_PMA_10GBT_SNR	133	/* 10GBASE-T SNR margin, lane A.
					 * Lanes B-D are numbered 134-136. */
#define MDIO_PMA_10GBR_FSRT_CSR	147	/* 10GBASE-R fast retrain status and control */
#define MDIO_PMA_10GBR_FECABLE	170	/* 10GBASE-R FEC ability */
#define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2	33	/* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL	32	/* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */
#define MDIO_B10L_PMA_CTRL	2294	/* 10BASE-T1L PMA control */
#define MDIO_PMA_10T1L_STAT	2295	/* 10BASE-T1L PMA status */
#define MDIO_PCS_10T1L_CTRL	2278	/* 10BASE-T1L PCS control */
#define MDIO_PMA_PMD_BT1	18	/* BASE-T1 PMA/PMD extended ability */
#define MDIO_AN_T1_CTRL		512	/* BASE-T1 AN control */
#define MDIO_AN_T1_STAT		513	/* BASE-T1 AN status */
#define MDIO_AN_T1_ADV_L	514	/* BASE-T1 AN advertisement register [15:0] */
#define MDIO_AN_T1_ADV_M	515	/* BASE-T1 AN advertisement register [31:16] */
#define MDIO_AN_T1_ADV_H	516	/* BASE-T1 AN advertisement register [47:32] */
#define MDIO_AN_T1_LP_L		517	/* BASE-T1 AN LP Base Page ability register [15:0] */
#define MDIO_AN_T1_LP_M		518	/* BASE-T1 AN LP Base Page ability register [31:16] */
#define MDIO_AN_T1_LP_H		519	/* BASE-T1 AN LP Base Page ability register [47:32] */
#define MDIO_AN_10BT1_AN_CTRL	526	/* 10BASE-T1 AN control register */
#define MDIO_AN_10BT1_AN_STAT	527	/* 10BASE-T1 AN status register */
#define MDIO_PMA_PMD_BT1_CTRL	2100	/* BASE-T1 PMA/PMD control register */
#define MDIO_PCS_1000BT1_CTRL	2304	/* 1000BASE-T1 PCS control register */
#define MDIO_PCS_1000BT1_STAT	2305	/* 1000BASE-T1 PCS status register */

/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
#define MDIO_PMA_LASI_TXCTRL	0x9001	/* TX_ALARM control */
#define MDIO_PMA_LASI_CTRL	0x9002	/* LASI control */
#define MDIO_PMA_LASI_RXSTAT	0x9003	/* RX_ALARM status */
#define MDIO_PMA_LASI_TXSTAT	0x9004	/* TX_ALARM status */
#define MDIO_PMA_LASI_STAT	0x9005	/* LASI status */

/* Control register 1. */
/* Enable extended speed selection */
#define MDIO_CTRL1_SPEEDSELEXT		(BMCR_SPEED1000 | BMCR_SPEED100)
/* All speed selection bits */
#define MDIO_CTRL1_SPEEDSEL		(MDIO_CTRL1_SPEEDSELEXT | 0x003c)
#define MDIO_CTRL1_FULLDPLX		BMCR_FULLDPLX
#define MDIO_CTRL1_LPOWER		BMCR_PDOWN
#define MDIO_CTRL1_RESET		BMCR_RESET
#define MDIO_PMA_CTRL1_LOOPBACK		0x0001
#define MDIO_PMA_CTRL1_SPEED1000	BMCR_SPEED1000
#define MDIO_PMA_CTRL1_SPEED100		BMCR_SPEED100
#define MDIO_PCS_CTRL1_LOOPBACK		BMCR_LOOPBACK
#define MDIO_PHYXS_CTRL1_LOOPBACK	BMCR_LOOPBACK
#define MDIO_AN_CTRL1_RESTART		BMCR_ANRESTART
#define MDIO_AN_CTRL1_ENABLE		BMCR_ANENABLE
#define MDIO_AN_CTRL1_XNP		0x2000	/* Enable extended next page */
#define MDIO_PCS_CTRL1_CLKSTOP_EN	0x400	/* Stop the clock during LPI */

/* 10 Gb/s */
#define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
/* 10PASS-TS/2BASE-TL */
#define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
/* 2.5 Gb/s */
#define MDIO_CTRL1_SPEED2_5G		(MDIO_CTRL1_SPEEDSELEXT | 0x18)
/* 5 Gb/s */
#define MDIO_CTRL1_SPEED5G		(MDIO_CTRL1_SPEEDSELEXT | 0x1c)

/* Status register 1. */
#define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
#define MDIO_STAT1_LSTATUS		BMSR_LSTATUS
#define MDIO_STAT1_FAULT		0x0080	/* Fault */
#define MDIO_AN_STAT1_LPABLE		0x0001	/* Link partner AN ability */
#define MDIO_AN_STAT1_ABLE		BMSR_ANEGCAPABLE
#define MDIO_AN_STAT1_RFAULT		BMSR_RFAULT
#define MDIO_AN_STAT1_COMPLETE		BMSR_ANEGCOMPLETE
#define MDIO_AN_STAT1_PAGE		0x0040	/* Page received */
#define MDIO_AN_STAT1_XNP		0x0080	/* Extended next page status */

/* Speed register. */
#define MDIO_SPEED_10G			0x0001	/* 10G capable */
#define MDIO_PMA_SPEED_2B		0x0002	/* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P		0x0004	/* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
#define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
#define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
#define MDIO_PMA_SPEED_2_5G		0x2000	/* 2.5G capable */
#define MDIO_PMA_SPEED_5G		0x4000	/* 5G capable */
#define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
#define MDIO_PCS_SPEED_2_5G		0x0040	/* 2.5G capable */
#define MDIO_PCS_SPEED_5G		0x0080	/* 5G capable */

/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
#define MDIO_DEVS_C22PRESENT		MDIO_DEVS_PRESENT(0)
#define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
#define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
#define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
#define MDIO_DEVS_PHYXS			MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
#define MDIO_DEVS_DTEXS			MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
#define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
#define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
#define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
#define MDIO_DEVS_VEND1			MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
#define MDIO_DEVS_VEND2			MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)

/* Control register 2. */
#define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
#define MDIO_PMA_CTRL2_10GBCX4		0x0000	/* 10GBASE-CX4 type */
#define MDIO_PMA_CTRL2_10GBEW		0x0001	/* 10GBASE-EW type */
#define MDIO_PMA_CTRL2_10GBLW		0x0002	/* 10GBASE-LW type */
#define MDIO_PMA_CTRL2_10GBSW		0x0003	/* 10GBASE-SW type */
#define MDIO_PMA_CTRL2_10GBLX4		0x0004	/* 10GBASE-LX4 type */
#define MDIO_PMA_CTRL2_10GBER		0x0005	/* 10GBASE-ER type */
#define MDIO_PMA_CTRL2_10GBLR		0x0006	/* 10GBASE-LR type */
#define MDIO_PMA_CTRL2_10GBSR		0x0007	/* 10GBASE-SR type */
#define MDIO_PMA_CTRL2_10GBLRM		0x0008	/* 10GBASE-LRM type */
#define MDIO_PMA_CTRL2_10GBT		0x0009	/* 10GBASE-T type */
#define MDIO_PMA_CTRL2_10GBKX4		0x000a	/* 10GBASE-KX4 type */
#define MDIO_PMA_CTRL2_10GBKR		0x000b	/* 10GBASE-KR type */
#define MDIO_PMA_CTRL2_1000BT		0x000c	/* 1000BASE-T type */
#define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
#define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
#define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
#define MDIO_PMA_CTRL2_2_5GBT		0x0030  /* 2.5GBaseT type */
#define MDIO_PMA_CTRL2_5GBT		0x0031  /* 5GBaseT type */
#define MDIO_PMA_CTRL2_BASET1		0x003D  /* BASE-T1 type */
#define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
#define MDIO_PCS_CTRL2_10GBW		0x0002	/* 10GBASE-W type */
#define MDIO_PCS_CTRL2_10GBT		0x0003	/* 10GBASE-T type */

/* Status register 2. */
#define MDIO_STAT2_RXFAULT		0x0400	/* Receive fault */
#define MDIO_STAT2_TXFAULT		0x0800	/* Transmit fault */
#define MDIO_STAT2_DEVPRST		0xc000	/* Device present */
#define MDIO_STAT2_DEVPRST_VAL		0x8000	/* Device present value */
#define MDIO_PMA_STAT2_LBABLE		0x0001	/* PMA loopback ability */
#define MDIO_PMA_STAT2_10GBEW		0x0002	/* 10GBASE-EW ability */
#define MDIO_PMA_STAT2_10GBLW		0x0004	/* 10GBASE-LW ability */
#define MDIO_PMA_STAT2_10GBSW		0x0008	/* 10GBASE-SW ability */
#define MDIO_PMA_STAT2_10GBLX4		0x0010	/* 10GBASE-LX4 ability */
#define MDIO_PMA_STAT2_10GBER		0x0020	/* 10GBASE-ER ability */
#define MDIO_PMA_STAT2_10GBLR		0x0040	/* 10GBASE-LR ability */
#define MDIO_PMA_STAT2_10GBSR		0x0080	/* 10GBASE-SR ability */
#define MDIO_PMD_STAT2_TXDISAB		0x0100	/* PMD TX disable ability */
#define MDIO_PMA_STAT2_EXTABLE		0x0200	/* Extended abilities */
#define MDIO_PMA_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
#define MDIO_PMA_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
#define MDIO_PCS_STAT2_10GBR		0x0001	/* 10GBASE-R capable */
#define MDIO_PCS_STAT2_10GBX		0x0002	/* 10GBASE-X capable */
#define MDIO_PCS_STAT2_10GBW		0x0004	/* 10GBASE-W capable */
#define MDIO_PCS_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
#define MDIO_PCS_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */

/* Transmit disable register. */
#define MDIO_PMD_TXDIS_GLOBAL		0x0001	/* Global PMD TX disable */
#define MDIO_PMD_TXDIS_0		0x0002	/* PMD TX disable 0 */
#define MDIO_PMD_TXDIS_1		0x0004	/* PMD TX disable 1 */
#define MDIO_PMD_TXDIS_2		0x0008	/* PMD TX disable 2 */
#define MDIO_PMD_TXDIS_3		0x0010	/* PMD TX disable 3 */

/* Receive signal detect register. */
#define MDIO_PMD_RXDET_GLOBAL		0x0001	/* Global PMD RX signal detect */
#define MDIO_PMD_RXDET_0		0x0002	/* PMD RX signal detect 0 */
#define MDIO_PMD_RXDET_1		0x0004	/* PMD RX signal detect 1 */
#define MDIO_PMD_RXDET_2		0x0008	/* PMD RX signal detect 2 */
#define MDIO_PMD_RXDET_3		0x0010	/* PMD RX signal detect 3 */

/* Extended abilities register. */
#define MDIO_PMA_EXTABLE_10GCX4		0x0001	/* 10GBASE-CX4 ability */
#define MDIO_PMA_EXTABLE_10GBLRM	0x0002	/* 10GBASE-LRM ability */
#define MDIO_PMA_EXTABLE_10GBT		0x0004	/* 10GBASE-T ability */
#define MDIO_PMA_EXTABLE_10GBKX4	0x0008	/* 10GBASE-KX4 ability */
#define MDIO_PMA_EXTABLE_10GBKR		0x0010	/* 10GBASE-KR ability */
#define MDIO_PMA_EXTABLE_1000BT		0x0020	/* 1000BASE-T ability */
#define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
#define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
#define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
#define MDIO_PMA_EXTABLE_BT1		0x0800	/* BASE-T1 ability */
#define MDIO_PMA_EXTABLE_NBT		0x4000  /* 2.5/5GBASE-T ability */

/* AN Clause 73 linkword */
#define MDIO_AN_C73_0_S_MASK		GENMASK(4, 0)
#define MDIO_AN_C73_0_E_MASK		GENMASK(9, 5)
#define MDIO_AN_C73_0_PAUSE		BIT(10)
#define MDIO_AN_C73_0_ASM_DIR		BIT(11)
#define MDIO_AN_C73_0_C2		BIT(12)
#define MDIO_AN_C73_0_RF		BIT(13)
#define MDIO_AN_C73_0_ACK		BIT(14)
#define MDIO_AN_C73_0_NP		BIT(15)
#define MDIO_AN_C73_1_T_MASK		GENMASK(4, 0)
#define MDIO_AN_C73_1_1000BASE_KX	BIT(5)
#define MDIO_AN_C73_1_10GBASE_KX4	BIT(6)
#define MDIO_AN_C73_1_10GBASE_KR	BIT(7)
#define MDIO_AN_C73_1_40GBASE_KR4	BIT(8)
#define MDIO_AN_C73_1_40GBASE_CR4	BIT(9)
#define MDIO_AN_C73_1_100GBASE_CR10	BIT(10)
#define MDIO_AN_C73_1_100GBASE_KP4	BIT(11)
#define MDIO_AN_C73_1_100GBASE_KR4	BIT(12)
#define MDIO_AN_C73_1_100GBASE_CR4	BIT(13)
#define MDIO_AN_C73_1_25GBASE_R_S	BIT(14)
#define MDIO_AN_C73_1_25GBASE_R		BIT(15)
#define MDIO_AN_C73_2_2500BASE_KX	BIT(0)
#define MDIO_AN_C73_2_5GBASE_KR		BIT(1)

/* PHY XGXS lane state register. */
#define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1		0x0002
#define MDIO_PHYXS_LNSTAT_SYNC2		0x0004
#define MDIO_PHYXS_LNSTAT_SYNC3		0x0008
#define MDIO_PHYXS_LNSTAT_ALIGN		0x1000

/* PMA 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_SWAPPOL_ABNX	0x0001	/* Pair A/B uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_CDNX	0x0002	/* Pair C/D uncrossed */
#define MDIO_PMA_10GBT_SWAPPOL_AREV	0x0100	/* Pair A polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_BREV	0x0200	/* Pair B polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_CREV	0x0400	/* Pair C polarity reversed */
#define MDIO_PMA_10GBT_SWAPPOL_DREV	0x0800	/* Pair D polarity reversed */

/* PMA 10GBASE-T TX power register. */
#define MDIO_PMA_10GBT_TXPWR_SHORT	0x0001	/* Short-reach mode */

/* PMA 10GBASE-T SNR registers. */
/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
#define MDIO_PMA_10GBT_SNR_BIAS		0x8000
#define MDIO_PMA_10GBT_SNR_MAX		127

/* PMA 10GBASE-R FEC ability register. */
#define MDIO_PMA_10GBR_FECABLE_ABLE	0x0001	/* FEC ability */
#define MDIO_PMA_10GBR_FECABLE_ERRABLE	0x0002	/* FEC error indic. ability */

/* PMA 10GBASE-R Fast Retrain status and control register. */
#define MDIO_PMA_10GBR_FSRT_ENABLE	0x0001	/* Fast retrain enable */

/* PCS 10GBASE-R/-T status register 1. */
#define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */

/* PCS 10GBASE-R/-T status register 2. */
#define MDIO_PCS_10GBRT_STAT2_ERR	0x00ff
#define MDIO_PCS_10GBRT_STAT2_BER	0x3f00

/* AN 10GBASE-T control register. */
#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G	0x0020	/* Advertise 2.5GBASE-T fast retrain */
#define MDIO_AN_10GBT_CTRL_ADV2_5G	0x0080	/* Advertise 2.5GBASE-T */
#define MDIO_AN_10GBT_CTRL_ADV5G	0x0100	/* Advertise 5GBASE-T */
#define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */

/* AN 10GBASE-T status register. */
#define MDIO_AN_10GBT_STAT_LP2_5G	0x0020  /* LP is 2.5GBT capable */
#define MDIO_AN_10GBT_STAT_LP5G		0x0040  /* LP is 5GBT capable */
#define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
#define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
#define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
#define MDIO_AN_10GBT_STAT_REMOK	0x1000	/* Remote OK */
#define MDIO_AN_10GBT_STAT_LOCOK	0x2000	/* Local OK */
#define MDIO_AN_10GBT_STAT_MS		0x4000	/* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT	0x8000	/* Master/slave config fault */

/* 10BASE-T1L PMA control */
#define MDIO_PMA_10T1L_CTRL_LB_EN	0x0001	/* Enable loopback mode */
#define MDIO_PMA_10T1L_CTRL_EEE_EN	0x0400	/* Enable EEE mode */
#define MDIO_PMA_10T1L_CTRL_LOW_POWER	0x0800	/* Low-power mode */
#define MDIO_PMA_10T1L_CTRL_2V4_EN	0x1000	/* Enable 2.4 Vpp operating mode */
#define MDIO_PMA_10T1L_CTRL_TX_DIS	0x4000	/* Transmit disable */
#define MDIO_PMA_10T1L_CTRL_PMA_RST	0x8000	/* MA reset */

/* 10BASE-T1L PMA status register. */
#define MDIO_PMA_10T1L_STAT_LINK	0x0001	/* PMA receive link up */
#define MDIO_PMA_10T1L_STAT_FAULT	0x0002	/* Fault condition detected */
#define MDIO_PMA_10T1L_STAT_POLARITY	0x0004	/* Receive polarity is reversed */
#define MDIO_PMA_10T1L_STAT_RECV_FAULT	0x0200	/* Able to detect fault on receive path */
#define MDIO_PMA_10T1L_STAT_EEE		0x0400	/* PHY has EEE ability */
#define MDIO_PMA_10T1L_STAT_LOW_POWER	0x0800	/* PMA has low-power ability */
#define MDIO_PMA_10T1L_STAT_2V4_ABLE	0x1000	/* PHY has 2.4 Vpp operating mode ability */
#define MDIO_PMA_10T1L_STAT_LB_ABLE	0x2000	/* PHY has loopback ability */

/* 10BASE-T1L PCS control register. */
#define MDIO_PCS_10T1L_CTRL_LB		0x4000	/* Enable PCS level loopback mode */
#define MDIO_PCS_10T1L_CTRL_RESET	0x8000	/* PCS reset */

/* BASE-T1 PMA/PMD extended ability register. */
#define MDIO_PMA_PMD_BT1_B100_ABLE	0x0001	/* 100BASE-T1 Ability */
#define MDIO_PMA_PMD_BT1_B1000_ABLE	0x0002	/* 1000BASE-T1 Ability */
#define MDIO_PMA_PMD_BT1_B10L_ABLE	0x0004	/* 10BASE-T1L Ability */

/* BASE-T1 auto-negotiation advertisement register [15:0] */
#define MDIO_AN_T1_ADV_L_PAUSE_CAP	ADVERTISE_PAUSE_CAP
#define MDIO_AN_T1_ADV_L_PAUSE_ASYM	ADVERTISE_PAUSE_ASYM
#define MDIO_AN_T1_ADV_L_FORCE_MS	0x1000	/* Force Master/slave Configuration */
#define MDIO_AN_T1_ADV_L_REMOTE_FAULT	ADVERTISE_RFAULT
#define MDIO_AN_T1_ADV_L_ACK		ADVERTISE_LPACK
#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ	ADVERTISE_NPAGE

/* BASE-T1 auto-negotiation advertisement register [31:16] */
#define MDIO_AN_T1_ADV_M_B10L		0x4000	/* device is compatible with 10BASE-T1L */
#define MDIO_AN_T1_ADV_M_1000BT1	0x0080	/* advertise 1000BASE-T1 */
#define MDIO_AN_T1_ADV_M_100BT1		0x0020	/* advertise 100BASE-T1 */
#define MDIO_AN_T1_ADV_M_MST		0x0010	/* advertise master preference */

/* BASE-T1 auto-negotiation advertisement register [47:32] */
#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ	0x1000	/* 10BASE-T1L High Level Transmit Request */
#define MDIO_AN_T1_ADV_H_10L_TX_HI	0x2000	/* 10BASE-T1L High Level Transmit Ability */

/* BASE-T1 AN LP Base Page ability register [15:0] */
#define MDIO_AN_T1_LP_L_PAUSE_CAP	LPA_PAUSE_CAP
#define MDIO_AN_T1_LP_L_PAUSE_ASYM	LPA_PAUSE_ASYM
#define MDIO_AN_T1_LP_L_FORCE_MS	0x1000	/* LP Force Master/slave Configuration */
#define MDIO_AN_T1_LP_L_REMOTE_FAULT	LPA_RFAULT
#define MDIO_AN_T1_LP_L_ACK		LPA_LPACK
#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ	LPA_NPAGE

/* BASE-T1 AN LP Base Page ability register [31:16] */
#define MDIO_AN_T1_LP_M_MST		0x0010	/* LP master preference */
#define MDIO_AN_T1_LP_M_B10L		0x4000	/* LP is compatible with 10BASE-T1L */

/* BASE-T1 AN LP Base Page ability register [47:32] */
#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ	0x1000	/* 10BASE-T1L High Level LP Transmit Request */
#define MDIO_AN_T1_LP_H_10L_TX_HI	0x2000	/* 10BASE-T1L High Level LP Transmit Ability */

/* 10BASE-T1 AN control register */
#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L	0x4000 /* 10BASE-T1L EEE ability advertisement */

/* 10BASE-T1 AN status register */
#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L	0x4000 /* 10BASE-T1L LP EEE ability advertisement */

/* BASE-T1 PMA/PMD control register */
#define MDIO_PMA_PMD_BT1_CTRL_STRAP		0x000F /* Type selection (Strap) */
#define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000	0x0001 /* Select 1000BASE-T1 */
#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST		0x4000 /* MASTER-SLAVE config value */

/* 1000BASE-T1 PCS control register */
#define MDIO_PCS_1000BT1_CTRL_LOW_POWER		0x0800 /* Low power mode */
#define MDIO_PCS_1000BT1_CTRL_DISABLE_TX	0x4000 /* Global PMA transmit disable */
#define MDIO_PCS_1000BT1_CTRL_RESET		0x8000 /* Software reset value */

/* 1000BASE-T1 PCS status register */
#define MDIO_PCS_1000BT1_STAT_LINK	0x0004 /* PCS Link is up */
#define MDIO_PCS_1000BT1_STAT_FAULT	0x0080 /* There is a fault condition */

/* EEE Supported/Advertisement/LP Advertisement registers.
 *
 * EEE capability Register (3.20), Advertisement (7.60) and
 * Link partner ability (7.61) registers have and can use the same identical
 * bit masks.
 */
#define MDIO_AN_EEE_ADV_100TX	0x0002	/* Advertise 100TX EEE cap */
#define MDIO_AN_EEE_ADV_1000T	0x0004	/* Advertise 1000T EEE cap */
/* Note: the two defines above can be potentially used by the user-land
 * and cannot remove them now.
 * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
 * using the previous ones (that can be considered obsolete).
 */
#define MDIO_EEE_100TX		MDIO_AN_EEE_ADV_100TX	/* 100TX EEE cap */
#define MDIO_EEE_1000T		MDIO_AN_EEE_ADV_1000T	/* 1000T EEE cap */
#define MDIO_EEE_10GT		0x0008	/* 10GT EEE cap */
#define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */
#define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
#define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
#define MDIO_EEE_40GR_FW	0x0100	/* 40G R fast wake */
#define MDIO_EEE_40GR_DS	0x0200	/* 40G R deep sleep */
#define MDIO_EEE_100GR_FW	0x1000	/* 100G R fast wake */
#define MDIO_EEE_100GR_DS	0x2000	/* 100G R deep sleep */

#define MDIO_EEE_2_5GT		0x0001	/* 2.5GT EEE cap */
#define MDIO_EEE_5GT		0x0002	/* 5GT EEE cap */

/* AN MultiGBASE-T AN control 2 */
#define MDIO_AN_THP_BP2_5GT	0x0008	/* 2.5GT THP bypass request */

/* 2.5G/5G Extended abilities register. */
#define MDIO_PMA_NG_EXTABLE_2_5GBT	0x0001	/* 2.5GBASET ability */
#define MDIO_PMA_NG_EXTABLE_5GBT	0x0002	/* 5GBASET ability */

/* LASI RX_ALARM control/status registers. */
#define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
#define MDIO_PMA_LASI_RX_PCSLFLT	0x0008	/* PCS RX local fault */
#define MDIO_PMA_LASI_RX_PMALFLT	0x0010	/* PMA/PMD RX local fault */
#define MDIO_PMA_LASI_RX_OPTICPOWERFLT	0x0020	/* RX optical power fault */
#define MDIO_PMA_LASI_RX_WISLFLT	0x0200	/* WIS local fault */

/* LASI TX_ALARM control/status registers. */
#define MDIO_PMA_LASI_TX_PHYXSLFLT	0x0001	/* PHY XS TX local fault */
#define MDIO_PMA_LASI_TX_PCSLFLT	0x0008	/* PCS TX local fault */
#define MDIO_PMA_LASI_TX_PMALFLT	0x0010	/* PMA/PMD TX local fault */
#define MDIO_PMA_LASI_TX_LASERPOWERFLT	0x0080	/* Laser output power fault */
#define MDIO_PMA_LASI_TX_LASERTEMPFLT	0x0100	/* Laser temperature fault */
#define MDIO_PMA_LASI_TX_LASERBICURRFLT	0x0200	/* Laser bias current fault */

/* LASI control/status registers. */
#define MDIO_PMA_LASI_LSALARM		0x0001	/* LS_ALARM enable/status */
#define MDIO_PMA_LASI_TXALARM		0x0002	/* TX_ALARM enable/status */
#define MDIO_PMA_LASI_RXALARM		0x0004	/* RX_ALARM enable/status */

/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */

#define MDIO_PHY_ID_C45			0x8000
#define MDIO_PHY_ID_PRTAD		0x03e0
#define MDIO_PHY_ID_DEVAD		0x001f
#define MDIO_PHY_ID_C45_MASK						\
	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)

static __inline__ __u16 mdio_phy_id_c45(int prtad, int devad)
{
	return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
}

/* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
#define MDIO_USXGMII_EEE_CLK_STP	0x0080	/* EEE clock stop supported */
#define MDIO_USXGMII_EEE		0x0100	/* EEE supported */
#define MDIO_USXGMII_SPD_MASK		0x0e00	/* USXGMII speed mask */
#define MDIO_USXGMII_FULL_DUPLEX	0x1000	/* USXGMII full duplex */
#define MDIO_USXGMII_DPX_SPD_MASK	0x1e00	/* USXGMII duplex and speed bits */
#define MDIO_USXGMII_10			0x0000	/* 10Mbps */
#define MDIO_USXGMII_10HALF		0x0000	/* 10Mbps half-duplex */
#define MDIO_USXGMII_10FULL		0x1000	/* 10Mbps full-duplex */
#define MDIO_USXGMII_100		0x0200	/* 100Mbps */
#define MDIO_USXGMII_100HALF		0x0200	/* 100Mbps half-duplex */
#define MDIO_USXGMII_100FULL		0x1200	/* 100Mbps full-duplex */
#define MDIO_USXGMII_1000		0x0400	/* 1000Mbps */
#define MDIO_USXGMII_1000HALF		0x0400	/* 1000Mbps half-duplex */
#define MDIO_USXGMII_1000FULL		0x1400	/* 1000Mbps full-duplex */
#define MDIO_USXGMII_10G		0x0600	/* 10Gbps */
#define MDIO_USXGMII_10GHALF		0x0600	/* 10Gbps half-duplex */
#define MDIO_USXGMII_10GFULL		0x1600	/* 10Gbps full-duplex */
#define MDIO_USXGMII_2500		0x0800	/* 2500Mbps */
#define MDIO_USXGMII_2500HALF		0x0800	/* 2500Mbps half-duplex */
#define MDIO_USXGMII_2500FULL		0x1800	/* 2500Mbps full-duplex */
#define MDIO_USXGMII_5000		0x0a00	/* 5000Mbps */
#define MDIO_USXGMII_5000HALF		0x0a00	/* 5000Mbps half-duplex */
#define MDIO_USXGMII_5000FULL		0x1a00	/* 5000Mbps full-duplex */
#define MDIO_USXGMII_LINK		0x8000	/* PHY link with copper-side partner */

#endif /* __LINUX_MDIO_H__ */

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