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..
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a.out.h
(6.73 KB)
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acct.h
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acrn.h
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adb.h
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adfs_fs.h
(993 B)
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affs_hardblocks.h
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agpgart.h
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aio_abi.h
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am437x-vpfe.h
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android
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apm_bios.h
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arcfb.h
(213 B)
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arm_sdei.h
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aspeed-lpc-ctrl.h
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aspeed-p2a-ctrl.h
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atalk.h
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atm.h
(7.7 KB)
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atm_eni.h
(648 B)
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atm_he.h
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atm_idt77105.h
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atm_nicstar.h
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atm_tcp.h
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atm_zatm.h
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atmapi.h
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atmarp.h
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atmbr2684.h
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atmclip.h
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atmdev.h
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atmioc.h
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atmlec.h
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atmmpc.h
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atmppp.h
(639 B)
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atmsap.h
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atmsvc.h
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audit.h
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auto_dev-ioctl.h
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auto_fs.h
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auto_fs4.h
(451 B)
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auxvec.h
(1.56 KB)
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ax25.h
(2.76 KB)
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batadv_packet.h
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batman_adv.h
(16.49 KB)
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baycom.h
(883 B)
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bcm933xx_hcs.h
(419 B)
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bfs_fs.h
(1.86 KB)
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binfmts.h
(776 B)
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bits.h
(447 B)
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blkpg.h
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blktrace_api.h
(4.59 KB)
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blkzoned.h
(6.34 KB)
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bpf.h
(272.11 KB)
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bpf_common.h
(1.33 KB)
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bpf_perf_event.h
(529 B)
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bpfilter.h
(465 B)
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bpqether.h
(981 B)
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bsg.h
(2.44 KB)
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bt-bmc.h
(572 B)
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btf.h
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btrfs.h
(29.85 KB)
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btrfs_tree.h
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byteorder
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cachefiles.h
(1.61 KB)
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caif
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can
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can.h
(11.23 KB)
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capability.h
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capi.h
(3.05 KB)
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cciss_defs.h
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cciss_ioctl.h
(2.7 KB)
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ccs.h
(767 B)
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cdrom.h
(28.87 KB)
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cec-funcs.h
(53.14 KB)
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cec.h
(40.47 KB)
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cfm_bridge.h
(1.42 KB)
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cgroupstats.h
(2.17 KB)
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chio.h
(5.16 KB)
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cifs
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close_range.h
(377 B)
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cm4000_cs.h
(1.76 KB)
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cn_proc.h
(4.05 KB)
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coda.h
(17.79 KB)
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coff.h
(12.25 KB)
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connector.h
(2.2 KB)
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const.h
(987 B)
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coresight-stm.h
(747 B)
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cramfs_fs.h
(3.47 KB)
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cryptouser.h
(5.2 KB)
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cuda.h
(905 B)
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cxl_mem.h
(7.73 KB)
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cycx_cfm.h
(2.92 KB)
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dcbnl.h
(24.7 KB)
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dccp.h
(6.29 KB)
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devlink.h
(22.77 KB)
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dlm.h
(2.49 KB)
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dlm_device.h
(2.48 KB)
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dlm_netlink.h
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dlm_plock.h
(894 B)
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dlmconstants.h
(4.96 KB)
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dm-ioctl.h
(11.48 KB)
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dm-log-userspace.h
(14.83 KB)
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dma-buf.h
(5.12 KB)
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dma-heap.h
(1.36 KB)
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dn.h
(4.53 KB)
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dns_resolver.h
(3.86 KB)
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dpll.h
(8.56 KB)
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dqblk_xfs.h
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dvb
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edd.h
(5.47 KB)
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efs_fs_sb.h
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elf-em.h
(2.57 KB)
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elf-fdpic.h
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elf.h
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errno.h
(23 B)
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errqueue.h
(1.94 KB)
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erspan.h
(1.03 KB)
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ethtool.h
(101.42 KB)
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ethtool_netlink.h
(6.17 KB)
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ethtool_netlink_generated.h
(19.17 KB)
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eventfd.h
(264 B)
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eventpoll.h
(2.84 KB)
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f2fs.h
(3.22 KB)
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fadvise.h
(842 B)
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falloc.h
(3.56 KB)
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fanotify.h
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fb.h
(16.09 KB)
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fcntl.h
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fd.h
(11.83 KB)
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fdreg.h
(5.24 KB)
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fib_rules.h
(1.99 KB)
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fiemap.h
(2.71 KB)
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filter.h
(2.16 KB)
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firewire-cdev.h
(43.2 KB)
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firewire-constants.h
(3.16 KB)
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fou.h
(819 B)
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fpga-dfl.h
(8.52 KB)
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fs.h
(12.88 KB)
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fscrypt.h
(6.41 KB)
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fsi.h
(2.2 KB)
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fsl_hypervisor.h
(7.13 KB)
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fsl_mc.h
(734 B)
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fsmap.h
(4.29 KB)
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fsverity.h
(3.11 KB)
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fuse.h
(25.36 KB)
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futex.h
(5.98 KB)
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gameport.h
(897 B)
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gen_stats.h
(1.49 KB)
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genetlink.h
(2.19 KB)
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genwqe
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gfs2_ondisk.h
(14.43 KB)
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gpio.h
(19.46 KB)
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gsmmux.h
(4.4 KB)
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gtp.h
(734 B)
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handshake.h
(1.61 KB)
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hash_info.h
(971 B)
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hdlc
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hdlc.h
(637 B)
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hdlcdrv.h
(2.84 KB)
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hdreg.h
(22.17 KB)
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hid.h
(2.04 KB)
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hiddev.h
(6.2 KB)
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hidraw.h
(1.95 KB)
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hpet.h
(743 B)
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hsi
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hsr_netlink.h
(1.08 KB)
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hw_breakpoint.h
(742 B)
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hyperv.h
(10.89 KB)
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i2c-dev.h
(1.83 KB)
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i2c.h
(6.73 KB)
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i2o-dev.h
(11.28 KB)
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i8k.h
(1.49 KB)
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icmp.h
(4.67 KB)
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icmpv6.h
(4.2 KB)
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idxd.h
(9.11 KB)
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if.h
(10.67 KB)
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if_addr.h
(1.84 KB)
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if_addrlabel.h
(721 B)
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if_alg.h
(1.53 KB)
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if_arcnet.h
(3.63 KB)
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if_arp.h
(6.41 KB)
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if_bonding.h
(5.02 KB)
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if_bridge.h
(20.27 KB)
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if_cablemodem.h
(986 B)
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if_eql.h
(1.32 KB)
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if_ether.h
(8.21 KB)
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if_fc.h
(1.7 KB)
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if_fddi.h
(4.27 KB)
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if_hippi.h
(4.14 KB)
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if_infiniband.h
(1.22 KB)
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if_link.h
(52.92 KB)
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if_ltalk.h
(210 B)
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if_macsec.h
(6.35 KB)
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if_packet.h
(7.99 KB)
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if_phonet.h
(424 B)
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if_plip.h
(660 B)
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if_ppp.h
(29 B)
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if_pppol2tp.h
(3.23 KB)
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if_pppox.h
(4.76 KB)
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if_slip.h
(872 B)
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if_team.h
(2.54 KB)
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if_tun.h
(4 KB)
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if_tunnel.h
(5.36 KB)
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if_vlan.h
(1.79 KB)
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if_x25.h
(881 B)
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if_xdp.h
(5.29 KB)
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ife.h
(351 B)
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igmp.h
(2.99 KB)
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iio
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ila.h
(1.22 KB)
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in.h
(10.24 KB)
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in6.h
(7.36 KB)
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in_route.h
(936 B)
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inet_diag.h
(4.9 KB)
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inotify.h
(3.21 KB)
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input-event-codes.h
(29.5 KB)
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input.h
(15.84 KB)
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io_uring.h
(20.4 KB)
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ioctl.h
(163 B)
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iommufd.h
(36.45 KB)
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ioprio.h
(4.08 KB)
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ip.h
(4.7 KB)
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ip6_tunnel.h
(1.91 KB)
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ip_vs.h
(13.8 KB)
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ipc.h
(2.05 KB)
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ipmi.h
(15.08 KB)
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ipmi_bmc.h
(488 B)
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ipmi_msgdefs.h
(3.35 KB)
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ipmi_ssif_bmc.h
(441 B)
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ipsec.h
(947 B)
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ipv6.h
(4.07 KB)
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ipv6_route.h
(1.86 KB)
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ipx.h
(2.29 KB)
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irqnr.h
(104 B)
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isdn
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iso_fs.h
(6.33 KB)
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isst_if.h
(14.92 KB)
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ivtv.h
(2.95 KB)
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ivtvfb.h
(1.18 KB)
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jffs2.h
(6.66 KB)
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joystick.h
(3.35 KB)
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kcm.h
(822 B)
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kcmp.h
(522 B)
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kcov.h
(1.92 KB)
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kd.h
(6.3 KB)
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kdev_t.h
(383 B)
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kernel-page-flags.h
(900 B)
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kernel.h
(194 B)
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kernelcapi.h
(1019 B)
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kexec.h
(2.05 KB)
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keyboard.h
(13.14 KB)
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keyctl.h
(5.86 KB)
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kfd_ioctl.h
(57.06 KB)
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kfd_sysfs.h
(5.25 KB)
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kvm.h
(47.24 KB)
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kvm_para.h
(1001 B)
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l2tp.h
(5.61 KB)
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landlock.h
(11.55 KB)
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libc-compat.h
(8.09 KB)
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limits.h
(937 B)
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lirc.h
(7.95 KB)
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llc.h
(3.09 KB)
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loadpin.h
(834 B)
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loop.h
(3.32 KB)
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lp.h
(4.09 KB)
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lsm.h
(1.51 KB)
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lwtunnel.h
(2.31 KB)
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magic.h
(3.73 KB)
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major.h
(4.55 KB)
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map_to_7segment.h
(6.45 KB)
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matroxfb.h
(1.43 KB)
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max2175.h
(1.01 KB)
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mdio.h
(23.78 KB)
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media-bus-format.h
(6.75 KB)
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media.h
(12.46 KB)
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mei.h
(3.4 KB)
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mei_uuid.h
(738 B)
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membarrier.h
(9.14 KB)
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memfd.h
(1.43 KB)
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mempolicy.h
(2.51 KB)
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meye.h
(2.47 KB)
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mii.h
(9.27 KB)
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minix_fs.h
(2.07 KB)
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misc
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mman.h
(1.75 KB)
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mmc
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mmtimer.h
(2.07 KB)
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module.h
(293 B)
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mount.h
(4.9 KB)
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mpls.h
(2.25 KB)
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mpls_iptunnel.h
(761 B)
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mptcp.h
(3.67 KB)
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mptcp_pm.h
(4.3 KB)
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mqueue.h
(2.15 KB)
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mroute.h
(5.78 KB)
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mroute6.h
(4.81 KB)
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mrp_bridge.h
(1.67 KB)
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msdos_fs.h
(6.57 KB)
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msg.h
(3.31 KB)
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mshv.h
(7.93 KB)
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mtio.h
(7.98 KB)
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nbd-netlink.h
(2.35 KB)
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nbd.h
(3.77 KB)
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ncsi.h
(4.71 KB)
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ndctl.h
(6.67 KB)
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neighbour.h
(5.91 KB)
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net.h
(2.04 KB)
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net_dropmon.h
(2.85 KB)
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net_namespace.h
(715 B)
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net_shaper.h
(2.52 KB)
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net_tstamp.h
(6.3 KB)
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netconf.h
(614 B)
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netdev.h
(5.65 KB)
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netdevice.h
(2.2 KB)
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netfilter
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netfilter.h
(1.69 KB)
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netfilter_arp
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netfilter_arp.h
(445 B)
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netfilter_bridge
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netfilter_bridge.h
(1.14 KB)
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netfilter_decnet.h
(1.72 KB)
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netfilter_ipv4
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netfilter_ipv4.h
(1.45 KB)
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netfilter_ipv6
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netfilter_ipv6.h
(1.35 KB)
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netlink.h
(12.09 KB)
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netlink_diag.h
(1.49 KB)
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netrom.h
(807 B)
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nexthop.h
(3.97 KB)
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nfc.h
(10.95 KB)
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nfs.h
(4.36 KB)
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nfs2.h
(1.43 KB)
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nfs3.h
(2.4 KB)
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nfs4.h
(6.54 KB)
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nfs4_mount.h
(1.89 KB)
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nfs_fs.h
(1.62 KB)
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nfs_idmap.h
(2.19 KB)
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nfs_mount.h
(2.09 KB)
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nfsacl.h
(718 B)
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nfsd
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nfsd_netlink.h
(1.95 KB)
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nilfs2_api.h
(7.41 KB)
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nilfs2_ondisk.h
(17.66 KB)
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nitro_enclaves.h
(12.85 KB)
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nl80211.h
(341.33 KB)
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nsfs.h
(639 B)
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nubus.h
(8 KB)
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nvme_ioctl.h
(2.43 KB)
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nvram.h
(532 B)
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omap3isp.h
(20.36 KB)
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omapfb.h
(5.78 KB)
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oom.h
(511 B)
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openat2.h
(1.42 KB)
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openvswitch.h
(40.75 KB)
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packet_diag.h
(1.63 KB)
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param.h
(141 B)
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parport.h
(3.56 KB)
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patchkey.h
(892 B)
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pci.h
(1.35 KB)
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pci_regs.h
(61.89 KB)
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pcitest.h
(920 B)
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perf_event.h
(42.68 KB)
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personality.h
(2.05 KB)
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pfkeyv2.h
(10.32 KB)
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pfrut.h
(7.8 KB)
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pg.h
(2.34 KB)
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phantom.h
(1.62 KB)
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phonet.h
(4.57 KB)
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pidfd.h
(256 B)
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pkt_cls.h
(18.65 KB)
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pkt_sched.h
(28.75 KB)
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pktcdvd.h
(2.63 KB)
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pmu.h
(5.32 KB)
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poll.h
(22 B)
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posix_acl.h
(1.22 KB)
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posix_acl_xattr.h
(1.09 KB)
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posix_types.h
(1.07 KB)
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ppdev.h
(3.21 KB)
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ppp-comp.h
(2.47 KB)
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ppp-ioctl.h
(5.59 KB)
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ppp_defs.h
(5.43 KB)
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pps.h
(4.62 KB)
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pr.h
(1.59 KB)
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prctl.h
(10.81 KB)
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psample.h
(2.57 KB)
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psci.h
(5.21 KB)
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psp-dbc.h
(5.16 KB)
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psp-sev.h
(7.59 KB)
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ptp_clock.h
(7.35 KB)
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ptrace.h
(4.29 KB)
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qemu_fw_cfg.h
(2.41 KB)
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qnx4_fs.h
(2.27 KB)
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qnxtypes.h
(624 B)
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qrtr.h
(893 B)
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quota.h
(6.16 KB)
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radeonfb.h
(360 B)
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raid
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random.h
(1.38 KB)
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rds.h
(10.91 KB)
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reboot.h
(1.31 KB)
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reiserfs_fs.h
(775 B)
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reiserfs_xattr.h
(533 B)
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remoteproc_cdev.h
(1.08 KB)
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resource.h
(2.32 KB)
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rfkill.h
(6.45 KB)
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rio_cm_cdev.h
(3.17 KB)
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rio_mport_cdev.h
(9.11 KB)
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rkisp1-config.h
(30.63 KB)
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romfs_fs.h
(1.21 KB)
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rose.h
(2.18 KB)
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route.h
(2.28 KB)
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rpl.h
(814 B)
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rpl_iptunnel.h
(424 B)
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rpmsg.h
(1.03 KB)
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rpmsg_types.h
(288 B)
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rseq.h
(4.79 KB)
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rtc.h
(5.19 KB)
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rtnetlink.h
(20.8 KB)
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rxrpc.h
(4.81 KB)
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scc.h
(4.52 KB)
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sched
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sched.h
(6.12 KB)
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scif_ioctl.h
(6.23 KB)
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screen_info.h
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Editing: iommufd.h
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. */ #ifndef _IOMMUFD_H #define _IOMMUFD_H #include <linux/ioctl.h> #include <linux/types.h> #define IOMMUFD_TYPE (';') /** * DOC: General ioctl format * * The ioctl interface follows a general format to allow for extensibility. Each * ioctl is passed in a structure pointer as the argument providing the size of * the structure in the first u32. The kernel checks that any structure space * beyond what it understands is 0. This allows userspace to use the backward * compatible portion while consistently using the newer, larger, structures. * * ioctls use a standard meaning for common errnos: * * - ENOTTY: The IOCTL number itself is not supported at all * - E2BIG: The IOCTL number is supported, but the provided structure has * non-zero in a part the kernel does not understand. * - EOPNOTSUPP: The IOCTL number is supported, and the structure is * understood, however a known field has a value the kernel does not * understand or support. * - EINVAL: Everything about the IOCTL was understood, but a field is not * correct. * - ENOENT: An ID or IOVA provided does not exist. * - ENOMEM: Out of memory. * - EOVERFLOW: Mathematics overflowed. * * As well as additional errnos, within specific ioctls. */ enum { IOMMUFD_CMD_BASE = 0x80, IOMMUFD_CMD_DESTROY = IOMMUFD_CMD_BASE, IOMMUFD_CMD_IOAS_ALLOC = 0x81, IOMMUFD_CMD_IOAS_ALLOW_IOVAS = 0x82, IOMMUFD_CMD_IOAS_COPY = 0x83, IOMMUFD_CMD_IOAS_IOVA_RANGES = 0x84, IOMMUFD_CMD_IOAS_MAP = 0x85, IOMMUFD_CMD_IOAS_UNMAP = 0x86, IOMMUFD_CMD_OPTION = 0x87, IOMMUFD_CMD_VFIO_IOAS = 0x88, IOMMUFD_CMD_HWPT_ALLOC = 0x89, IOMMUFD_CMD_GET_HW_INFO = 0x8a, IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING = 0x8b, IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP = 0x8c, IOMMUFD_CMD_HWPT_INVALIDATE = 0x8d, IOMMUFD_CMD_FAULT_QUEUE_ALLOC = 0x8e, IOMMUFD_CMD_IOAS_MAP_FILE = 0x8f, IOMMUFD_CMD_VIOMMU_ALLOC = 0x90, IOMMUFD_CMD_VDEVICE_ALLOC = 0x91, IOMMUFD_CMD_IOAS_CHANGE_PROCESS = 0x92, }; /** * struct iommu_destroy - ioctl(IOMMU_DESTROY) * @size: sizeof(struct iommu_destroy) * @id: iommufd object ID to destroy. Can be any destroyable object type. * * Destroy any object held within iommufd. */ struct iommu_destroy { __u32 size; __u32 id; }; #define IOMMU_DESTROY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_DESTROY) /** * struct iommu_ioas_alloc - ioctl(IOMMU_IOAS_ALLOC) * @size: sizeof(struct iommu_ioas_alloc) * @flags: Must be 0 * @out_ioas_id: Output IOAS ID for the allocated object * * Allocate an IO Address Space (IOAS) which holds an IO Virtual Address (IOVA) * to memory mapping. */ struct iommu_ioas_alloc { __u32 size; __u32 flags; __u32 out_ioas_id; }; #define IOMMU_IOAS_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_ALLOC) /** * struct iommu_iova_range - ioctl(IOMMU_IOVA_RANGE) * @start: First IOVA * @last: Inclusive last IOVA * * An interval in IOVA space. */ struct iommu_iova_range { __aligned_u64 start; __aligned_u64 last; }; /** * struct iommu_ioas_iova_ranges - ioctl(IOMMU_IOAS_IOVA_RANGES) * @size: sizeof(struct iommu_ioas_iova_ranges) * @ioas_id: IOAS ID to read ranges from * @num_iovas: Input/Output total number of ranges in the IOAS * @__reserved: Must be 0 * @allowed_iovas: Pointer to the output array of struct iommu_iova_range * @out_iova_alignment: Minimum alignment required for mapping IOVA * * Query an IOAS for ranges of allowed IOVAs. Mapping IOVA outside these ranges * is not allowed. num_iovas will be set to the total number of iovas and * the allowed_iovas[] will be filled in as space permits. * * The allowed ranges are dependent on the HW path the DMA operation takes, and * can change during the lifetime of the IOAS. A fresh empty IOAS will have a * full range, and each attached device will narrow the ranges based on that * device's HW restrictions. Detaching a device can widen the ranges. Userspace * should query ranges after every attach/detach to know what IOVAs are valid * for mapping. * * On input num_iovas is the length of the allowed_iovas array. On output it is * the total number of iovas filled in. The ioctl will return -EMSGSIZE and set * num_iovas to the required value if num_iovas is too small. In this case the * caller should allocate a larger output array and re-issue the ioctl. * * out_iova_alignment returns the minimum IOVA alignment that can be given * to IOMMU_IOAS_MAP/COPY. IOVA's must satisfy:: * * starting_iova % out_iova_alignment == 0 * (starting_iova + length) % out_iova_alignment == 0 * * out_iova_alignment can be 1 indicating any IOVA is allowed. It cannot * be higher than the system PAGE_SIZE. */ struct iommu_ioas_iova_ranges { __u32 size; __u32 ioas_id; __u32 num_iovas; __u32 __reserved; __aligned_u64 allowed_iovas; __aligned_u64 out_iova_alignment; }; #define IOMMU_IOAS_IOVA_RANGES _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_IOVA_RANGES) /** * struct iommu_ioas_allow_iovas - ioctl(IOMMU_IOAS_ALLOW_IOVAS) * @size: sizeof(struct iommu_ioas_allow_iovas) * @ioas_id: IOAS ID to allow IOVAs from * @num_iovas: Input/Output total number of ranges in the IOAS * @__reserved: Must be 0 * @allowed_iovas: Pointer to array of struct iommu_iova_range * * Ensure a range of IOVAs are always available for allocation. If this call * succeeds then IOMMU_IOAS_IOVA_RANGES will never return a list of IOVA ranges * that are narrower than the ranges provided here. This call will fail if * IOMMU_IOAS_IOVA_RANGES is currently narrower than the given ranges. * * When an IOAS is first created the IOVA_RANGES will be maximally sized, and as * devices are attached the IOVA will narrow based on the device restrictions. * When an allowed range is specified any narrowing will be refused, ie device * attachment can fail if the device requires limiting within the allowed range. * * Automatic IOVA allocation is also impacted by this call. MAP will only * allocate within the allowed IOVAs if they are present. * * This call replaces the entire allowed list with the given list. */ struct iommu_ioas_allow_iovas { __u32 size; __u32 ioas_id; __u32 num_iovas; __u32 __reserved; __aligned_u64 allowed_iovas; }; #define IOMMU_IOAS_ALLOW_IOVAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_ALLOW_IOVAS) /** * enum iommufd_ioas_map_flags - Flags for map and copy * @IOMMU_IOAS_MAP_FIXED_IOVA: If clear the kernel will compute an appropriate * IOVA to place the mapping at * @IOMMU_IOAS_MAP_WRITEABLE: DMA is allowed to write to this mapping * @IOMMU_IOAS_MAP_READABLE: DMA is allowed to read from this mapping */ enum iommufd_ioas_map_flags { IOMMU_IOAS_MAP_FIXED_IOVA = 1 << 0, IOMMU_IOAS_MAP_WRITEABLE = 1 << 1, IOMMU_IOAS_MAP_READABLE = 1 << 2, }; /** * struct iommu_ioas_map - ioctl(IOMMU_IOAS_MAP) * @size: sizeof(struct iommu_ioas_map) * @flags: Combination of enum iommufd_ioas_map_flags * @ioas_id: IOAS ID to change the mapping of * @__reserved: Must be 0 * @user_va: Userspace pointer to start mapping from * @length: Number of bytes to map * @iova: IOVA the mapping was placed at. If IOMMU_IOAS_MAP_FIXED_IOVA is set * then this must be provided as input. * * Set an IOVA mapping from a user pointer. If FIXED_IOVA is specified then the * mapping will be established at iova, otherwise a suitable location based on * the reserved and allowed lists will be automatically selected and returned in * iova. * * If IOMMU_IOAS_MAP_FIXED_IOVA is specified then the iova range must currently * be unused, existing IOVA cannot be replaced. */ struct iommu_ioas_map { __u32 size; __u32 flags; __u32 ioas_id; __u32 __reserved; __aligned_u64 user_va; __aligned_u64 length; __aligned_u64 iova; }; #define IOMMU_IOAS_MAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP) /** * struct iommu_ioas_map_file - ioctl(IOMMU_IOAS_MAP_FILE) * @size: sizeof(struct iommu_ioas_map_file) * @flags: same as for iommu_ioas_map * @ioas_id: same as for iommu_ioas_map * @fd: the memfd to map * @start: byte offset from start of file to map from * @length: same as for iommu_ioas_map * @iova: same as for iommu_ioas_map * * Set an IOVA mapping from a memfd file. All other arguments and semantics * match those of IOMMU_IOAS_MAP. */ struct iommu_ioas_map_file { __u32 size; __u32 flags; __u32 ioas_id; __s32 fd; __aligned_u64 start; __aligned_u64 length; __aligned_u64 iova; }; #define IOMMU_IOAS_MAP_FILE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP_FILE) /** * struct iommu_ioas_copy - ioctl(IOMMU_IOAS_COPY) * @size: sizeof(struct iommu_ioas_copy) * @flags: Combination of enum iommufd_ioas_map_flags * @dst_ioas_id: IOAS ID to change the mapping of * @src_ioas_id: IOAS ID to copy from * @length: Number of bytes to copy and map * @dst_iova: IOVA the mapping was placed at. If IOMMU_IOAS_MAP_FIXED_IOVA is * set then this must be provided as input. * @src_iova: IOVA to start the copy * * Copy an already existing mapping from src_ioas_id and establish it in * dst_ioas_id. The src iova/length must exactly match a range used with * IOMMU_IOAS_MAP. * * This may be used to efficiently clone a subset of an IOAS to another, or as a * kind of 'cache' to speed up mapping. Copy has an efficiency advantage over * establishing equivalent new mappings, as internal resources are shared, and * the kernel will pin the user memory only once. */ struct iommu_ioas_copy { __u32 size; __u32 flags; __u32 dst_ioas_id; __u32 src_ioas_id; __aligned_u64 length; __aligned_u64 dst_iova; __aligned_u64 src_iova; }; #define IOMMU_IOAS_COPY _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_COPY) /** * struct iommu_ioas_unmap - ioctl(IOMMU_IOAS_UNMAP) * @size: sizeof(struct iommu_ioas_unmap) * @ioas_id: IOAS ID to change the mapping of * @iova: IOVA to start the unmapping at * @length: Number of bytes to unmap, and return back the bytes unmapped * * Unmap an IOVA range. The iova/length must be a superset of a previously * mapped range used with IOMMU_IOAS_MAP or IOMMU_IOAS_COPY. Splitting or * truncating ranges is not allowed. The values 0 to U64_MAX will unmap * everything. */ struct iommu_ioas_unmap { __u32 size; __u32 ioas_id; __aligned_u64 iova; __aligned_u64 length; }; #define IOMMU_IOAS_UNMAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_UNMAP) /** * enum iommufd_option - ioctl(IOMMU_OPTION_RLIMIT_MODE) and * ioctl(IOMMU_OPTION_HUGE_PAGES) * @IOMMU_OPTION_RLIMIT_MODE: * Change how RLIMIT_MEMLOCK accounting works. The caller must have privilege * to invoke this. Value 0 (default) is user based accounting, 1 uses process * based accounting. Global option, object_id must be 0 * @IOMMU_OPTION_HUGE_PAGES: * Value 1 (default) allows contiguous pages to be combined when generating * iommu mappings. Value 0 disables combining, everything is mapped to * PAGE_SIZE. This can be useful for benchmarking. This is a per-IOAS * option, the object_id must be the IOAS ID. */ enum iommufd_option { IOMMU_OPTION_RLIMIT_MODE = 0, IOMMU_OPTION_HUGE_PAGES = 1, }; /** * enum iommufd_option_ops - ioctl(IOMMU_OPTION_OP_SET) and * ioctl(IOMMU_OPTION_OP_GET) * @IOMMU_OPTION_OP_SET: Set the option's value * @IOMMU_OPTION_OP_GET: Get the option's value */ enum iommufd_option_ops { IOMMU_OPTION_OP_SET = 0, IOMMU_OPTION_OP_GET = 1, }; /** * struct iommu_option - iommu option multiplexer * @size: sizeof(struct iommu_option) * @option_id: One of enum iommufd_option * @op: One of enum iommufd_option_ops * @__reserved: Must be 0 * @object_id: ID of the object if required * @val64: Option value to set or value returned on get * * Change a simple option value. This multiplexor allows controlling options * on objects. IOMMU_OPTION_OP_SET will load an option and IOMMU_OPTION_OP_GET * will return the current value. */ struct iommu_option { __u32 size; __u32 option_id; __u16 op; __u16 __reserved; __u32 object_id; __aligned_u64 val64; }; #define IOMMU_OPTION _IO(IOMMUFD_TYPE, IOMMUFD_CMD_OPTION) /** * enum iommufd_vfio_ioas_op - IOMMU_VFIO_IOAS_* ioctls * @IOMMU_VFIO_IOAS_GET: Get the current compatibility IOAS * @IOMMU_VFIO_IOAS_SET: Change the current compatibility IOAS * @IOMMU_VFIO_IOAS_CLEAR: Disable VFIO compatibility */ enum iommufd_vfio_ioas_op { IOMMU_VFIO_IOAS_GET = 0, IOMMU_VFIO_IOAS_SET = 1, IOMMU_VFIO_IOAS_CLEAR = 2, }; /** * struct iommu_vfio_ioas - ioctl(IOMMU_VFIO_IOAS) * @size: sizeof(struct iommu_vfio_ioas) * @ioas_id: For IOMMU_VFIO_IOAS_SET the input IOAS ID to set * For IOMMU_VFIO_IOAS_GET will output the IOAS ID * @op: One of enum iommufd_vfio_ioas_op * @__reserved: Must be 0 * * The VFIO compatibility support uses a single ioas because VFIO APIs do not * support the ID field. Set or Get the IOAS that VFIO compatibility will use. * When VFIO_GROUP_SET_CONTAINER is used on an iommufd it will get the * compatibility ioas, either by taking what is already set, or auto creating * one. From then on VFIO will continue to use that ioas and is not effected by * this ioctl. SET or CLEAR does not destroy any auto-created IOAS. */ struct iommu_vfio_ioas { __u32 size; __u32 ioas_id; __u16 op; __u16 __reserved; }; #define IOMMU_VFIO_IOAS _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VFIO_IOAS) /** * enum iommufd_hwpt_alloc_flags - Flags for HWPT allocation * @IOMMU_HWPT_ALLOC_NEST_PARENT: If set, allocate a HWPT that can serve as * the parent HWPT in a nesting configuration. * @IOMMU_HWPT_ALLOC_DIRTY_TRACKING: Dirty tracking support for device IOMMU is * enforced on device attachment * @IOMMU_HWPT_FAULT_ID_VALID: The fault_id field of hwpt allocation data is * valid. * @IOMMU_HWPT_ALLOC_PASID: Requests a domain that can be used with PASID. The * domain can be attached to any PASID on the device. * Any domain attached to the non-PASID part of the * device must also be flagged, otherwise attaching a * PASID will blocked. * If IOMMU does not support PASID it will return * error (-EOPNOTSUPP). */ enum iommufd_hwpt_alloc_flags { IOMMU_HWPT_ALLOC_NEST_PARENT = 1 << 0, IOMMU_HWPT_ALLOC_DIRTY_TRACKING = 1 << 1, IOMMU_HWPT_FAULT_ID_VALID = 1 << 2, IOMMU_HWPT_ALLOC_PASID = 1 << 3, }; /** * enum iommu_hwpt_vtd_s1_flags - Intel VT-d stage-1 page table * entry attributes * @IOMMU_VTD_S1_SRE: Supervisor request * @IOMMU_VTD_S1_EAFE: Extended access enable * @IOMMU_VTD_S1_WPE: Write protect enable */ enum iommu_hwpt_vtd_s1_flags { IOMMU_VTD_S1_SRE = 1 << 0, IOMMU_VTD_S1_EAFE = 1 << 1, IOMMU_VTD_S1_WPE = 1 << 2, }; /** * struct iommu_hwpt_vtd_s1 - Intel VT-d stage-1 page table * info (IOMMU_HWPT_DATA_VTD_S1) * @flags: Combination of enum iommu_hwpt_vtd_s1_flags * @pgtbl_addr: The base address of the stage-1 page table. * @addr_width: The address width of the stage-1 page table * @__reserved: Must be 0 */ struct iommu_hwpt_vtd_s1 { __aligned_u64 flags; __aligned_u64 pgtbl_addr; __u32 addr_width; __u32 __reserved; }; /** * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 nested STE * (IOMMU_HWPT_DATA_ARM_SMMUV3) * * @ste: The first two double words of the user space Stream Table Entry for * the translation. Must be little-endian. * Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec) * - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax * - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD * * -EIO will be returned if @ste is not legal or contains any non-allowed field. * Cfg can be used to select a S1, Bypass or Abort configuration. A Bypass * nested domain will translate the same as the nesting parent. The S1 will * install a Context Descriptor Table pointing at userspace memory translated * by the nesting parent. */ struct iommu_hwpt_arm_smmuv3 { __aligned_le64 ste[2]; }; /** * enum iommu_hwpt_data_type - IOMMU HWPT Data Type * @IOMMU_HWPT_DATA_NONE: no data * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table * @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table */ enum iommu_hwpt_data_type { IOMMU_HWPT_DATA_NONE = 0, IOMMU_HWPT_DATA_VTD_S1 = 1, IOMMU_HWPT_DATA_ARM_SMMUV3 = 2, }; /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) * @flags: Combination of enum iommufd_hwpt_alloc_flags * @dev_id: The device to allocate this HWPT for * @pt_id: The IOAS or HWPT or vIOMMU to connect this HWPT to * @out_hwpt_id: The ID of the new HWPT * @__reserved: Must be 0 * @data_type: One of enum iommu_hwpt_data_type * @data_len: Length of the type specific data * @data_uptr: User pointer to the type specific data * @fault_id: The ID of IOMMUFD_FAULT object. Valid only if flags field of * IOMMU_HWPT_FAULT_ID_VALID is set. * @__reserved2: Padding to 64-bit alignment. Must be 0. * * Explicitly allocate a hardware page table object. This is the same object * type that is returned by iommufd_device_attach() and represents the * underlying iommu driver's iommu_domain kernel object. * * A kernel-managed HWPT will be created with the mappings from the given * IOAS via the @pt_id. The @data_type for this allocation must be set to * IOMMU_HWPT_DATA_NONE. The HWPT can be allocated as a parent HWPT for a * nesting configuration by passing IOMMU_HWPT_ALLOC_NEST_PARENT via @flags. * * A user-managed nested HWPT will be created from a given vIOMMU (wrapping a * parent HWPT) or a parent HWPT via @pt_id, in which the parent HWPT must be * allocated previously via the same ioctl from a given IOAS (@pt_id). In this * case, the @data_type must be set to a pre-defined type corresponding to an * I/O page table type supported by the underlying IOMMU hardware. The device * via @dev_id and the vIOMMU via @pt_id must be associated to the same IOMMU * instance. * * If the @data_type is set to IOMMU_HWPT_DATA_NONE, @data_len and * @data_uptr should be zero. Otherwise, both @data_len and @data_uptr * must be given. */ struct iommu_hwpt_alloc { __u32 size; __u32 flags; __u32 dev_id; __u32 pt_id; __u32 out_hwpt_id; __u32 __reserved; __u32 data_type; __u32 data_len; __aligned_u64 data_uptr; __u32 fault_id; __u32 __reserved2; }; #define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC) /** * enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info * @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings * on a nested_parent domain. * https://www.intel.com/content/www/us/en/content-details/772415/content-details.html */ enum iommu_hw_info_vtd_flags { IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0, }; /** * struct iommu_hw_info_vtd - Intel VT-d hardware information * * @flags: Combination of enum iommu_hw_info_vtd_flags * @__reserved: Must be 0 * * @cap_reg: Value of Intel VT-d capability register defined in VT-d spec * section 11.4.2 Capability Register. * @ecap_reg: Value of Intel VT-d capability register defined in VT-d spec * section 11.4.3 Extended Capability Register. * * User needs to understand the Intel VT-d specification to decode the * register value. */ struct iommu_hw_info_vtd { __u32 flags; __u32 __reserved; __aligned_u64 cap_reg; __aligned_u64 ecap_reg; }; /** * struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information * (IOMMU_HW_INFO_TYPE_ARM_SMMUV3) * * @flags: Must be set to 0 * @__reserved: Must be 0 * @idr: Implemented features for ARM SMMU Non-secure programming interface * @iidr: Information about the implementation and implementer of ARM SMMU, * and architecture version supported * @aidr: ARM SMMU architecture version * * For the details of @idr, @iidr and @aidr, please refer to the chapters * from 6.3.1 to 6.3.6 in the SMMUv3 Spec. * * This reports the raw HW capability, and not all bits are meaningful to be * read by userspace. Only the following fields should be used: * * idr[0]: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN , CD2L, ASID16, TTF * idr[1]: SIDSIZE, SSIDSIZE * idr[3]: BBML, RIL * idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K * * - S1P should be assumed to be true if a NESTED HWPT can be created * - VFIO/iommufd only support platforms with COHACC, it should be assumed to be * true. * - ATS is a per-device property. If the VMM describes any devices as ATS * capable in ACPI/DT it should set the corresponding idr. * * This list may expand in future (eg E0PD, AIE, PBHA, D128, DS etc). It is * important that VMMs do not read bits outside the list to allow for * compatibility with future kernels. Several features in the SMMUv3 * architecture are not currently supported by the kernel for nesting: HTTU, * BTM, MPAM and others. */ struct iommu_hw_info_arm_smmuv3 { __u32 flags; __u32 __reserved; __u32 idr[6]; __u32 iidr; __u32 aidr; }; /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_NONE: Used by the drivers that do not report hardware * info * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE = 0, IOMMU_HW_INFO_TYPE_INTEL_VTD = 1, IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, }; /** * enum iommufd_hw_capabilities * @IOMMU_HW_CAP_DIRTY_TRACKING: IOMMU hardware support for dirty tracking * If available, it means the following APIs * are supported: * * IOMMU_HWPT_GET_DIRTY_BITMAP * IOMMU_HWPT_SET_DIRTY_TRACKING * */ enum iommufd_hw_capabilities { IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0, }; /** * struct iommu_hw_info - ioctl(IOMMU_GET_HW_INFO) * @size: sizeof(struct iommu_hw_info) * @flags: Must be 0 * @dev_id: The device bound to the iommufd * @data_len: Input the length of a user buffer in bytes. Output the length of * data that kernel supports * @data_uptr: User pointer to a user-space buffer used by the kernel to fill * the iommu type specific hardware information data * @out_data_type: Output the iommu hardware info type as defined in the enum * iommu_hw_info_type. * @out_capabilities: Output the generic iommu capability info type as defined * in the enum iommu_hw_capabilities. * @__reserved: Must be 0 * * Query an iommu type specific hardware information data from an iommu behind * a given device that has been bound to iommufd. This hardware info data will * be used to sync capabilities between the virtual iommu and the physical * iommu, e.g. a nested translation setup needs to check the hardware info, so * a guest stage-1 page table can be compatible with the physical iommu. * * To capture an iommu type specific hardware information data, @data_uptr and * its length @data_len must be provided. Trailing bytes will be zeroed if the * user buffer is larger than the data that kernel has. Otherwise, kernel only * fills the buffer using the given length in @data_len. If the ioctl succeeds, * @data_len will be updated to the length that kernel actually supports, * @out_data_type will be filled to decode the data filled in the buffer * pointed by @data_uptr. Input @data_len == zero is allowed. */ struct iommu_hw_info { __u32 size; __u32 flags; __u32 dev_id; __u32 data_len; __aligned_u64 data_uptr; __u32 out_data_type; __u32 __reserved; __aligned_u64 out_capabilities; }; #define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO) /* * enum iommufd_hwpt_set_dirty_tracking_flags - Flags for steering dirty * tracking * @IOMMU_HWPT_DIRTY_TRACKING_ENABLE: Enable dirty tracking */ enum iommufd_hwpt_set_dirty_tracking_flags { IOMMU_HWPT_DIRTY_TRACKING_ENABLE = 1, }; /** * struct iommu_hwpt_set_dirty_tracking - ioctl(IOMMU_HWPT_SET_DIRTY_TRACKING) * @size: sizeof(struct iommu_hwpt_set_dirty_tracking) * @flags: Combination of enum iommufd_hwpt_set_dirty_tracking_flags * @hwpt_id: HW pagetable ID that represents the IOMMU domain * @__reserved: Must be 0 * * Toggle dirty tracking on an HW pagetable. */ struct iommu_hwpt_set_dirty_tracking { __u32 size; __u32 flags; __u32 hwpt_id; __u32 __reserved; }; #define IOMMU_HWPT_SET_DIRTY_TRACKING _IO(IOMMUFD_TYPE, \ IOMMUFD_CMD_HWPT_SET_DIRTY_TRACKING) /** * enum iommufd_hwpt_get_dirty_bitmap_flags - Flags for getting dirty bits * @IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR: Just read the PTEs without clearing * any dirty bits metadata. This flag * can be passed in the expectation * where the next operation is an unmap * of the same IOVA range. * */ enum iommufd_hwpt_get_dirty_bitmap_flags { IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR = 1, }; /** * struct iommu_hwpt_get_dirty_bitmap - ioctl(IOMMU_HWPT_GET_DIRTY_BITMAP) * @size: sizeof(struct iommu_hwpt_get_dirty_bitmap) * @hwpt_id: HW pagetable ID that represents the IOMMU domain * @flags: Combination of enum iommufd_hwpt_get_dirty_bitmap_flags * @__reserved: Must be 0 * @iova: base IOVA of the bitmap first bit * @length: IOVA range size * @page_size: page size granularity of each bit in the bitmap * @data: bitmap where to set the dirty bits. The bitmap bits each * represent a page_size which you deviate from an arbitrary iova. * * Checking a given IOVA is dirty: * * data[(iova / page_size) / 64] & (1ULL << ((iova / page_size) % 64)) * * Walk the IOMMU pagetables for a given IOVA range to return a bitmap * with the dirty IOVAs. In doing so it will also by default clear any * dirty bit metadata set in the IOPTE. */ struct iommu_hwpt_get_dirty_bitmap { __u32 size; __u32 hwpt_id; __u32 flags; __u32 __reserved; __aligned_u64 iova; __aligned_u64 length; __aligned_u64 page_size; __aligned_u64 data; }; #define IOMMU_HWPT_GET_DIRTY_BITMAP _IO(IOMMUFD_TYPE, \ IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP) /** * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation * Data Type * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1 * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3 */ enum iommu_hwpt_invalidate_data_type { IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0, IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1, }; /** * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d * stage-1 cache invalidation * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies * to all-levels page structure cache or just * the leaf PTE cache. */ enum iommu_hwpt_vtd_s1_invalidate_flags { IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0, }; /** * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation * (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1) * @addr: The start address of the range to be invalidated. It needs to * be 4KB aligned. * @npages: Number of contiguous 4K pages to be invalidated. * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags * @__reserved: Must be 0 * * The Intel VT-d specific invalidation data for user-managed stage-1 cache * invalidation in nested translation. Userspace uses this structure to * tell the impacted cache scope after modifying the stage-1 page table. * * Invalidating all the caches related to the page table by setting @addr * to be 0 and @npages to be U64_MAX. * * The device TLB will be invalidated automatically if ATS is enabled. */ struct iommu_hwpt_vtd_s1_invalidate { __aligned_u64 addr; __aligned_u64 npages; __u32 flags; __u32 __reserved; }; /** * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cache invalidation * (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3) * @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ. * Must be little-endian. * * Supported command list only when passing in a vIOMMU via @hwpt_id: * CMDQ_OP_TLBI_NSNH_ALL * CMDQ_OP_TLBI_NH_VA * CMDQ_OP_TLBI_NH_VAA * CMDQ_OP_TLBI_NH_ALL * CMDQ_OP_TLBI_NH_ASID * CMDQ_OP_ATC_INV * CMDQ_OP_CFGI_CD * CMDQ_OP_CFGI_CD_ALL * * -EIO will be returned if the command is not supported. */ struct iommu_viommu_arm_smmuv3_invalidate { __aligned_le64 cmd[2]; }; /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) * @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation * @data_uptr: User pointer to an array of driver-specific cache invalidation * data. * @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data * type of all the entries in the invalidation request array. It * should be a type supported by the hwpt pointed by @hwpt_id. * @entry_len: Length (in bytes) of a request entry in the request array * @entry_num: Input the number of cache invalidation requests in the array. * Output the number of requests successfully handled by kernel. * @__reserved: Must be 0. * * Invalidate iommu cache for user-managed page table or vIOMMU. Modifications * on a user-managed page table should be followed by this operation, if a HWPT * is passed in via @hwpt_id. Other caches, such as device cache or descriptor * cache can be flushed if a vIOMMU is passed in via the @hwpt_id field. * * Each ioctl can support one or more cache invalidation requests in the array * that has a total size of @entry_len * @entry_num. * * An empty invalidation request array by setting @entry_num==0 is allowed, and * @entry_len and @data_uptr would be ignored in this case. This can be used to * check if the given @data_type is supported or not by kernel. */ struct iommu_hwpt_invalidate { __u32 size; __u32 hwpt_id; __aligned_u64 data_uptr; __u32 data_type; __u32 entry_len; __u32 entry_num; __u32 __reserved; }; #define IOMMU_HWPT_INVALIDATE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_INVALIDATE) /** * enum iommu_hwpt_pgfault_flags - flags for struct iommu_hwpt_pgfault * @IOMMU_PGFAULT_FLAGS_PASID_VALID: The pasid field of the fault data is * valid. * @IOMMU_PGFAULT_FLAGS_LAST_PAGE: It's the last fault of a fault group. */ enum iommu_hwpt_pgfault_flags { IOMMU_PGFAULT_FLAGS_PASID_VALID = (1 << 0), IOMMU_PGFAULT_FLAGS_LAST_PAGE = (1 << 1), }; /** * enum iommu_hwpt_pgfault_perm - perm bits for struct iommu_hwpt_pgfault * @IOMMU_PGFAULT_PERM_READ: request for read permission * @IOMMU_PGFAULT_PERM_WRITE: request for write permission * @IOMMU_PGFAULT_PERM_EXEC: (PCIE 10.4.1) request with a PASID that has the * Execute Requested bit set in PASID TLP Prefix. * @IOMMU_PGFAULT_PERM_PRIV: (PCIE 10.4.1) request with a PASID that has the * Privileged Mode Requested bit set in PASID TLP * Prefix. */ enum iommu_hwpt_pgfault_perm { IOMMU_PGFAULT_PERM_READ = (1 << 0), IOMMU_PGFAULT_PERM_WRITE = (1 << 1), IOMMU_PGFAULT_PERM_EXEC = (1 << 2), IOMMU_PGFAULT_PERM_PRIV = (1 << 3), }; /** * struct iommu_hwpt_pgfault - iommu page fault data * @flags: Combination of enum iommu_hwpt_pgfault_flags * @dev_id: id of the originated device * @pasid: Process Address Space ID * @grpid: Page Request Group Index * @perm: Combination of enum iommu_hwpt_pgfault_perm * @__reserved: Must be 0. * @addr: Fault address * @length: a hint of how much data the requestor is expecting to fetch. For * example, if the PRI initiator knows it is going to do a 10MB * transfer, it could fill in 10MB and the OS could pre-fault in * 10MB of IOVA. It's default to 0 if there's no such hint. * @cookie: kernel-managed cookie identifying a group of fault messages. The * cookie number encoded in the last page fault of the group should * be echoed back in the response message. */ struct iommu_hwpt_pgfault { __u32 flags; __u32 dev_id; __u32 pasid; __u32 grpid; __u32 perm; __u32 __reserved; __aligned_u64 addr; __u32 length; __u32 cookie; }; /** * enum iommufd_page_response_code - Return status of fault handlers * @IOMMUFD_PAGE_RESP_SUCCESS: Fault has been handled and the page tables * populated, retry the access. This is the * "Success" defined in PCI 10.4.2.1. * @IOMMUFD_PAGE_RESP_INVALID: Could not handle this fault, don't retry the * access. This is the "Invalid Request" in PCI * 10.4.2.1. */ enum iommufd_page_response_code { IOMMUFD_PAGE_RESP_SUCCESS = 0, IOMMUFD_PAGE_RESP_INVALID = 1, }; /** * struct iommu_hwpt_page_response - IOMMU page fault response * @cookie: The kernel-managed cookie reported in the fault message. * @code: One of response code in enum iommufd_page_response_code. */ struct iommu_hwpt_page_response { __u32 cookie; __u32 code; }; /** * struct iommu_fault_alloc - ioctl(IOMMU_FAULT_QUEUE_ALLOC) * @size: sizeof(struct iommu_fault_alloc) * @flags: Must be 0 * @out_fault_id: The ID of the new FAULT * @out_fault_fd: The fd of the new FAULT * * Explicitly allocate a fault handling object. */ struct iommu_fault_alloc { __u32 size; __u32 flags; __u32 out_fault_id; __u32 out_fault_fd; }; #define IOMMU_FAULT_QUEUE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_FAULT_QUEUE_ALLOC) /** * enum iommu_viommu_type - Virtual IOMMU Type * @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1, }; /** * struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC) * @size: sizeof(struct iommu_viommu_alloc) * @flags: Must be 0 * @type: Type of the virtual IOMMU. Must be defined in enum iommu_viommu_type * @dev_id: The device's physical IOMMU will be used to back the virtual IOMMU * @hwpt_id: ID of a nesting parent HWPT to associate to * @out_viommu_id: Output virtual IOMMU ID for the allocated object * * Allocate a virtual IOMMU object, representing the underlying physical IOMMU's * virtualization support that is a security-isolated slice of the real IOMMU HW * that is unique to a specific VM. Operations global to the IOMMU are connected * to the vIOMMU, such as: * - Security namespace for guest owned ID, e.g. guest-controlled cache tags * - Non-device-affiliated event reporting, e.g. invalidation queue errors * - Access to a sharable nesting parent pagetable across physical IOMMUs * - Virtualization of various platforms IDs, e.g. RIDs and others * - Delivery of paravirtualized invalidation * - Direct assigned invalidation queues * - Direct assigned interrupts */ struct iommu_viommu_alloc { __u32 size; __u32 flags; __u32 type; __u32 dev_id; __u32 hwpt_id; __u32 out_viommu_id; }; #define IOMMU_VIOMMU_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VIOMMU_ALLOC) /** * struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC) * @size: sizeof(struct iommu_vdevice_alloc) * @viommu_id: vIOMMU ID to associate with the virtual device * @dev_id: The physical device to allocate a virtual instance on the vIOMMU * @out_vdevice_id: Object handle for the vDevice. Pass to IOMMU_DESTORY * @virt_id: Virtual device ID per vIOMMU, e.g. vSID of ARM SMMUv3, vDeviceID * of AMD IOMMU, and vRID of a nested Intel VT-d to a Context Table * * Allocate a virtual device instance (for a physical device) against a vIOMMU. * This instance holds the device's information (related to its vIOMMU) in a VM. */ struct iommu_vdevice_alloc { __u32 size; __u32 viommu_id; __u32 dev_id; __u32 out_vdevice_id; __aligned_u64 virt_id; }; #define IOMMU_VDEVICE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VDEVICE_ALLOC) /** * struct iommu_ioas_change_process - ioctl(VFIO_IOAS_CHANGE_PROCESS) * @size: sizeof(struct iommu_ioas_change_process) * @__reserved: Must be 0 * * This transfers pinned memory counts for every memory map in every IOAS * in the context to the current process. This only supports maps created * with IOMMU_IOAS_MAP_FILE, and returns EINVAL if other maps are present. * If the ioctl returns a failure status, then nothing is changed. * * This API is useful for transferring operation of a device from one process * to another, such as during userland live update. */ struct iommu_ioas_change_process { __u32 size; __u32 __reserved; }; #define IOMMU_IOAS_CHANGE_PROCESS \ _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_CHANGE_PROCESS) #endif
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